changeset fb8c44de891a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=fb8c44de891a
description:
mem: Add support for a security bit in the memory system
This patch adds the basic building blocks required to support e.g. ARM
TrustZone by discerning secure and non-secure memory accesses.
diffstat:
src/mem/cache/base.hh | 6 +-
src/mem/cache/blk.cc | 17 ++++-
src/mem/cache/blk.hh | 15 +++-
src/mem/cache/cache.hh | 23 +++---
src/mem/cache/cache_impl.hh | 134 +++++++++++++++++++++++---------------
src/mem/cache/mshr.cc | 16 ++--
src/mem/cache/mshr.hh | 3 +
src/mem/cache/mshr_queue.cc | 24 +++---
src/mem/cache/mshr_queue.hh | 10 ++-
src/mem/cache/prefetch/base.cc | 33 ++++++---
src/mem/cache/prefetch/base.hh | 6 +-
src/mem/cache/prefetch/ghb.cc | 24 ++++++-
src/mem/cache/prefetch/ghb.hh | 14 ++++
src/mem/cache/prefetch/stride.cc | 33 +++++++--
src/mem/cache/prefetch/stride.hh | 15 +++-
src/mem/cache/tags/cacheset.hh | 14 ++-
src/mem/cache/tags/fa_lru.cc | 5 +-
src/mem/cache/tags/fa_lru.hh | 7 +-
src/mem/cache/tags/lru.cc | 15 ++-
src/mem/cache/tags/lru.hh | 7 +-
src/mem/packet.cc | 8 +-
src/mem/packet.hh | 22 +++++-
src/mem/request.hh | 4 +
23 files changed, 311 insertions(+), 144 deletions(-)
diffs (truncated from 1337 to 300 lines):
diff -r 532929273927 -r fb8c44de891a src/mem/cache/base.hh
--- a/src/mem/cache/base.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/mem/cache/base.hh Fri Jan 24 15:29:30 2014 -0600
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -560,9 +560,9 @@
virtual unsigned int drain(DrainManager *dm);
- virtual bool inCache(Addr addr) const = 0;
+ virtual bool inCache(Addr addr, bool is_secure) const = 0;
- virtual bool inMissQueue(Addr addr) const = 0;
+ virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
void incMissCount(PacketPtr pkt)
{
diff -r 532929273927 -r fb8c44de891a src/mem/cache/blk.cc
--- a/src/mem/cache/blk.cc Fri Jan 24 15:29:30 2014 -0600
+++ b/src/mem/cache/blk.cc Fri Jan 24 15:29:30 2014 -0600
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012-2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2007 The Regents of The University of Michigan
* All rights reserved.
*
@@ -33,9 +45,10 @@
CacheBlkPrintWrapper::print(std::ostream &os, int verbosity,
const std::string &prefix) const
{
- ccprintf(os, "%sblk %c%c%c\n", prefix,
+ ccprintf(os, "%sblk %c%c%c%c\n", prefix,
blk->isValid() ? 'V' : '-',
blk->isWritable() ? 'E' : '-',
- blk->isDirty() ? 'M' : '-');
+ blk->isDirty() ? 'M' : '-',
+ blk->isSecure() ? 'S' : '-');
}
diff -r 532929273927 -r fb8c44de891a src/mem/cache/blk.hh
--- a/src/mem/cache/blk.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/mem/cache/blk.hh Fri Jan 24 15:29:30 2014 -0600
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -70,7 +70,9 @@
/** block was referenced */
BlkReferenced = 0x10,
/** block was a hardware prefetch yet unaccessed*/
- BlkHWPrefetched = 0x20
+ BlkHWPrefetched = 0x20,
+ /** block holds data from the secure memory space */
+ BlkSecure = 0x40
};
/**
@@ -263,6 +265,15 @@
}
/**
+ * Check if this block holds data from the secure memory space.
+ * @return True if the block holds data from the secure memory space.
+ */
+ bool isSecure() const
+ {
+ return (status & BlkSecure) != 0;
+ }
+
+ /**
* Track the fact that a local locked was issued to the block. If
* multiple LLs get issued from the same context we could have
* redundant records on the list, but that's OK, as they'll all
diff -r 532929273927 -r fb8c44de891a src/mem/cache/cache.hh
--- a/src/mem/cache/cache.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/mem/cache/cache.hh Fri Jan 24 15:29:30 2014 -0600
@@ -209,12 +209,13 @@
void cmpAndSwap(BlkType *blk, PacketPtr pkt);
/**
- * Find a block frame for new block at address addr, assuming that
- * the block is not currently in the cache. Append writebacks if
- * any to provided packet list. Return free block frame. May
- * return NULL if there are no replaceable blocks at the moment.
+ * Find a block frame for new block at address addr targeting the
+ * given security space, assuming that the block is not currently
+ * in the cache. Append writebacks if any to provided packet
+ * list. Return free block frame. May return NULL if there are
+ * no replaceable blocks at the moment.
*/
- BlkType *allocateBlock(Addr addr, PacketList &writebacks);
+ BlkType *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
/**
* Populates a cache block and handles all outstanding requests for the
@@ -384,16 +385,16 @@
return mshrQueue.allocated != 0;
}
- CacheBlk *findBlock(Addr addr) const {
- return tags->findBlock(addr);
+ CacheBlk *findBlock(Addr addr, bool is_secure) const {
+ return tags->findBlock(addr, is_secure);
}
- bool inCache(Addr addr) const {
- return (tags->findBlock(addr) != 0);
+ bool inCache(Addr addr, bool is_secure) const {
+ return (tags->findBlock(addr, is_secure) != 0);
}
- bool inMissQueue(Addr addr) const {
- return (mshrQueue.findMatch(addr) != 0);
+ bool inMissQueue(Addr addr, bool is_secure) const {
+ return (mshrQueue.findMatch(addr, is_secure) != 0);
}
/**
diff -r 532929273927 -r fb8c44de891a src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Fri Jan 24 15:29:30 2014 -0600
+++ b/src/mem/cache/cache_impl.hh Fri Jan 24 15:29:30 2014 -0600
@@ -301,11 +301,12 @@
}
int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
- blk = tags->accessBlock(pkt->getAddr(), lat, id);
+ blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id);
- DPRINTF(Cache, "%s%s %x %s %s\n", pkt->cmdString(),
+ DPRINTF(Cache, "%s%s %x (%s) %s %s\n", pkt->cmdString(),
pkt->req->isInstFetch() ? " (ifetch)" : "",
- pkt->getAddr(), blk ? "hit" : "miss", blk ? blk->print() : "");
+ pkt->getAddr(), pkt->isSecure() ? "s" : "ns",
+ blk ? "hit" : "miss", blk ? blk->print() : "");
if (blk != NULL) {
@@ -327,7 +328,7 @@
assert(blkSize == pkt->getSize());
if (blk == NULL) {
// need to do a replacement
- blk = allocateBlock(pkt->getAddr(), writebacks);
+ blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks);
if (blk == NULL) {
// no replaceable block available, give up.
// writeback will be forwarded to next level.
@@ -390,8 +391,8 @@
assert(pkt->cmd == MemCmd::HardPFResp);
// Check if it's a prefetch response and handle it. We shouldn't
// get any other kinds of responses without FRRs.
- DPRINTF(Cache, "Got prefetch response from above for addr %#x\n",
- pkt->getAddr());
+ DPRINTF(Cache, "Got prefetch response from above for addr %#x (%s)\n",
+ pkt->getAddr(), pkt->isSecure() ? "s" : "ns");
recvTimingResp(pkt);
return;
}
@@ -431,8 +432,8 @@
}
if (pkt->memInhibitAsserted()) {
- DPRINTF(Cache, "mem inhibited on 0x%x: not responding\n",
- pkt->getAddr());
+ DPRINTF(Cache, "mem inhibited on 0x%x (%s): not responding\n",
+ pkt->getAddr(), pkt->isSecure() ? "s" : "ns");
assert(!pkt->req->isUncacheable());
// Special tweak for multilevel coherence: snoop downward here
// on invalidates since there may be other caches below here
@@ -489,7 +490,8 @@
(pkt->cmd == MemCmd::WriteReq
|| pkt->cmd == MemCmd::WriteInvalidateReq) ) {
// not outstanding misses, can do this
- MSHR *outstanding_miss = mshrQueue.findMatch(pkt->getAddr());
+ MSHR *outstanding_miss = mshrQueue.findMatch(pkt->getAddr(),
+ pkt->isSecure());
if (pkt->cmd == MemCmd::WriteInvalidateReq || !outstanding_miss) {
if (outstanding_miss) {
warn("WriteInv doing a fastallocate"
@@ -532,7 +534,7 @@
pkt->busFirstWordDelay = pkt->busLastWordDelay = 0;
Addr blk_addr = blockAlign(pkt->getAddr());
- MSHR *mshr = mshrQueue.findMatch(blk_addr);
+ MSHR *mshr = mshrQueue.findMatch(blk_addr, pkt->isSecure());
if (mshr) {
/// MSHR hit
@@ -672,16 +674,19 @@
// have to invalidate ourselves and any lower caches even if
// upper cache will be responding
if (pkt->isInvalidate()) {
- BlkType *blk = tags->findBlock(pkt->getAddr());
+ BlkType *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
if (blk && blk->isValid()) {
tags->invalidate(blk);
blk->invalidate();
- DPRINTF(Cache, "rcvd mem-inhibited %s on 0x%x: invalidating\n",
- pkt->cmdString(), pkt->getAddr());
+ DPRINTF(Cache, "rcvd mem-inhibited %s on 0x%x (%s):"
+ " invalidating\n",
+ pkt->cmdString(), pkt->getAddr(),
+ pkt->isSecure() ? "s" : "ns");
}
if (!last_level_cache) {
- DPRINTF(Cache, "forwarding mem-inhibited %s on 0x%x\n",
- pkt->cmdString(), pkt->getAddr());
+ DPRINTF(Cache, "forwarding mem-inhibited %s on 0x%x (%s)\n",
+ pkt->cmdString(), pkt->getAddr(),
+ pkt->isSecure() ? "s" : "ns");
lat += ticksToCycles(memSidePort->sendAtomic(pkt));
}
} else {
@@ -711,8 +716,9 @@
bus_pkt = pkt;
}
- DPRINTF(Cache, "Sending an atomic %s for %x\n",
- bus_pkt->cmdString(), bus_pkt->getAddr());
+ DPRINTF(Cache, "Sending an atomic %s for %x (%s)\n",
+ bus_pkt->cmdString(), bus_pkt->getAddr(),
+ bus_pkt->isSecure() ? "s" : "ns");
#if TRACING_ON
CacheBlk::State old_state = blk ? blk->status : 0;
@@ -720,8 +726,10 @@
lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt));
- DPRINTF(Cache, "Receive response: %s for addr %x in state %i\n",
- bus_pkt->cmdString(), bus_pkt->getAddr(), old_state);
+ DPRINTF(Cache, "Receive response: %s for addr %x (%s) in state %i\n",
+ bus_pkt->cmdString(), bus_pkt->getAddr(),
+ bus_pkt->isSecure() ? "s" : "ns",
+ old_state);
// If packet was a forward, the response (if any) is already
// in place in the bus_pkt == pkt structure, so we don't need
@@ -794,8 +802,9 @@
}
Addr blk_addr = blockAlign(pkt->getAddr());
- BlkType *blk = tags->findBlock(pkt->getAddr());
- MSHR *mshr = mshrQueue.findMatch(blk_addr);
+ bool is_secure = pkt->isSecure();
+ BlkType *blk = tags->findBlock(pkt->getAddr(), is_secure);
+ MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
pkt->pushLabel(name());
@@ -808,7 +817,8 @@
// see if we have data at all (owned or otherwise)
bool have_data = blk && blk->isValid()
- && pkt->checkFunctional(&cbpw, blk_addr, blkSize, blk->data);
+ && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize,
+ blk->data);
// data we have is dirty if marked as such or if valid & ownership
// pending due to outstanding UpgradeReq
@@ -822,8 +832,8 @@
|| writeBuffer.checkFunctional(pkt, blk_addr)
|| memSidePort->checkFunctional(pkt);
- DPRINTF(Cache, "functional %s %x %s%s%s\n",
- pkt->cmdString(), pkt->getAddr(),
+ DPRINTF(Cache, "functional %s %x (%s) %s%s%s\n",
+ pkt->cmdString(), pkt->getAddr(), is_secure ? "s" : "ns",
(blk && blk->isValid()) ? "valid " : "",
have_data ? "data " : "", done ? "done " : "");
@@ -866,12 +876,13 @@
assert(mshr);
if (is_error) {
- DPRINTF(Cache, "Cache received packet with error for address %x, "
- "cmd: %s\n", pkt->getAddr(), pkt->cmdString());
+ DPRINTF(Cache, "Cache received packet with error for address %x (%s), "
+ "cmd: %s\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns",
+ pkt->cmdString());
}
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