[gem5-dev] changeset in gem5: cpu: Add support for Memory+Barrier instructi...

[Giacomo Gabrielli]

changeset 5a7852a013d4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5a7852a013d4
description:
        cpu: Add support for Memory+Barrier instruction types in O3 cpu.

diffstat:

 src/cpu/o3/inst_queue_impl.hh |  16 +++++++++++-----
 1 files changed, 11 insertions(+), 5 deletions(-)

diffs (32 lines):

diff -r 79d034cd6ba3 -r 5a7852a013d4 src/cpu/o3/inst_queue_impl.hh
--- a/src/cpu/o3/inst_queue_impl.hh     Fri Jan 24 15:29:30 2014 -0600
+++ b/src/cpu/o3/inst_queue_impl.hh     Fri Jan 24 15:29:30 2014 -0600
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011-2012 ARM Limited
+ * Copyright (c) 2011-2013 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved.
  *
@@ -1157,11 +1157,17 @@
             DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n",
                     tid, squashed_inst->seqNum, squashed_inst->pcState());
 
+            bool is_acq_rel = squashed_inst->isMemBarrier() &&
+                         (squashed_inst->isLoad() ||
+                           (squashed_inst->isStore() &&
+                             !squashed_inst->isStoreConditional()));
+
             // Remove the instruction from the dependency list.
-            if (!squashed_inst->isNonSpeculative() &&
-                !squashed_inst->isStoreConditional() &&
-                !squashed_inst->isMemBarrier() &&
-                !squashed_inst->isWriteBarrier()) {
+            if (is_acq_rel ||
+                (!squashed_inst->isNonSpeculative() &&
+                 !squashed_inst->isStoreConditional() &&
+                 !squashed_inst->isMemBarrier() &&
+                 !squashed_inst->isWriteBarrier())) {
 
                 for (int src_reg_idx = 0;
                      src_reg_idx < squashed_inst->numSrcRegs();
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