changeset 06a33d872798 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=06a33d872798
description:
mem: Add a wrapped DRAMSim2 memory controller
This patch adds DRAMSim2 as a memory controller by wrapping the
external library and creating a sublass of AbstractMemory that bridges
between the semantics of gem5 and the DRAMSim2 interface.
The DRAMSim2 wrapper extracts the clock period from the config
file. There is no way of extracting this information from DRAMSim2
itself, so we simply read the same config file and get it from there.
To properly model the response queue, the wrapper keeps track of how
many transactions are in the actual controller, and how many are
stacking up waiting to be sent back as responses (in the wrapper). The
latter requires us to move away from the queued port and manage the
packets ourselves. This is due to DRAMSim2 not having any flow control
on the response path.
DRAMSim2 assumes that the transactions it is given are matching the
burst size of the choosen memory. The wrapper checks to ensure the
cache line size of the system matches the burst size of DRAMSim2 as
there are currently no provisions to split the system requests. In
theory we could allow a cache line size smaller than the burst size,
but that would lead to inefficient use of the DRAM, so for not we
fatal also in this case.
diffstat:
.hgignore | 1 +
SConstruct | 4 +
configs/common/MemConfig.py | 1 +
ext/dramsim2/README | 11 +
ext/dramsim2/SConscript | 86 +++++++++
src/mem/DRAMSim2.py | 56 ++++++
src/mem/SConscript | 7 +
src/mem/dramsim2.cc | 410 ++++++++++++++++++++++++++++++++++++++++++++
src/mem/dramsim2.hh | 210 ++++++++++++++++++++++
src/mem/dramsim2_wrapper.cc | 199 +++++++++++++++++++++
src/mem/dramsim2_wrapper.hh | 163 +++++++++++++++++
11 files changed, 1148 insertions(+), 0 deletions(-)
diffs (truncated from 1220 to 300 lines):
diff -r 58bf21ca88de -r 06a33d872798 .hgignore
--- a/.hgignore Tue Feb 18 05:50:52 2014 -0500
+++ b/.hgignore Tue Feb 18 05:50:53 2014 -0500
@@ -9,3 +9,4 @@
.*.swp
m5out
src/doxygen
+ext/dramsim2/DRAMSim2
diff -r 58bf21ca88de -r 06a33d872798 SConstruct
--- a/SConstruct Tue Feb 18 05:50:52 2014 -0500
+++ b/SConstruct Tue Feb 18 05:50:53 2014 -0500
@@ -1154,6 +1154,10 @@
main.SConscript('ext/fputils/SConscript',
variant_dir = joinpath(build_root, 'fputils'))
+# DRAMSim2 build is shared across all configs in the build root.
+main.SConscript('ext/dramsim2/SConscript',
+ variant_dir = joinpath(build_root, 'dramsim2'))
+
###################################################
#
# This function is used to set up a directory with switching headers
diff -r 58bf21ca88de -r 06a33d872798 configs/common/MemConfig.py
--- a/configs/common/MemConfig.py Tue Feb 18 05:50:52 2014 -0500
+++ b/configs/common/MemConfig.py Tue Feb 18 05:50:53 2014 -0500
@@ -54,6 +54,7 @@
("lpddr2_s4_1066_x32", "LPDDR2_S4_1066_x32"),
("lpddr3_1600_x32", "LPDDR3_1600_x32"),
("wio_200_x128", "WideIO_200_x128"),
+ ("dramsim2", "DRAMSim2")
]
# Filtered list of aliases. Only aliases for existing memory
diff -r 58bf21ca88de -r 06a33d872798 ext/dramsim2/README
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/ext/dramsim2/README Tue Feb 18 05:50:53 2014 -0500
@@ -0,0 +1,11 @@
+Follow these steps to get DRAMSim2 as part of gem5
+
+1. Download DRAMSim2
+ 1.1 Go to ext/dramsim2 (this directory)
+ 1.2 Clone DRAMSim2: git clone git://github.com/dramninjasUMD/DRAMSim2.git
+
+2. Compile gem5
+ 2.1 Business as usual
+
+3. Run gem5 with DRAMSim2
+ 3.1 Use --mem-type=dramsim2 and set the device and system configuration
diff -r 58bf21ca88de -r 06a33d872798 ext/dramsim2/SConscript
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/ext/dramsim2/SConscript Tue Feb 18 05:50:53 2014 -0500
@@ -0,0 +1,86 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Hansson
+
+import os
+
+Import('main')
+
+# See if we got a cloned DRAMSim2 repo as a subdirectory and set the
+# HAVE_DRAMSIM flag accordingly
+if not os.path.exists(Dir('.').srcnode().abspath + '/DRAMSim2'):
+ main['HAVE_DRAMSIM'] = False
+ Return()
+
+# We have got the folder, so add the library and build the wrappers
+main['HAVE_DRAMSIM'] = True
+
+# Add the appropriate files. We leave out the trace driven simulator
+dram_files = []
+
+def DRAMFile(filename):
+ dram_files.append(File('DRAMSim2/' + filename))
+
+DRAMFile('AddressMapping.cpp')
+DRAMFile('Bank.cpp')
+DRAMFile('BankState.cpp')
+DRAMFile('BusPacket.cpp')
+DRAMFile('ClockDomain.cpp')
+DRAMFile('CommandQueue.cpp')
+DRAMFile('IniReader.cpp')
+DRAMFile('MemoryController.cpp')
+DRAMFile('MemorySystem.cpp')
+DRAMFile('MultiChannelMemorySystem.cpp')
+DRAMFile('Rank.cpp')
+DRAMFile('SimulatorObject.cpp')
+DRAMFile('Transaction.cpp')
+
+# DRAMSim2 violates some of the warning flags used by gem5, so
+# we explicitly disable them here
+dramenv = main.Clone()
+dramenv.Append(CCFLAGS=['-Wno-unused-value'])
+
+# Tell DRAMSim2 to not store any data as this is already covered by
+# the wrapper
+dramenv.Append(CCFLAGS=['-DNO_STORAGE'])
+
+dramenv.Library('dramsim2', [main.SharedObject(f) for f in dram_files])
+
+main.Prepend(CPPPATH=Dir('.'))
+main.Append(LIBS=['dramsim2'])
+main.Prepend(LIBPATH=[Dir('.')])
diff -r 58bf21ca88de -r 06a33d872798 src/mem/DRAMSim2.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/DRAMSim2.py Tue Feb 18 05:50:53 2014 -0500
@@ -0,0 +1,56 @@
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Hansson
+
+from m5.params import *
+from AbstractMemory import *
+
+# A wrapper for DRAMSim2 multi-channel memory controller
+class DRAMSim2(AbstractMemory):
+ type = 'DRAMSim2'
+ cxx_header = "mem/dramsim2.hh"
+
+ # A single port for now
+ port = SlavePort("Slave port")
+
+ deviceConfigFile = Param.String("ini/DDR3_micron_32M_8B_x8_sg15.ini",
+ "Device configuration file")
+ systemConfigFile = Param.String("system.ini.example",
+ "Memory organisation configuration file")
+ filePath = Param.String("ext/dramsim2/DRAMSim2/",
+ "Directory to prepend to file names")
+ traceFile = Param.String("", "Output file for trace generation")
+ enableDebug = Param.Bool(False, "Enable DRAMSim2 debug output")
diff -r 58bf21ca88de -r 06a33d872798 src/mem/SConscript
--- a/src/mem/SConscript Tue Feb 18 05:50:52 2014 -0500
+++ b/src/mem/SConscript Tue Feb 18 05:50:53 2014 -0500
@@ -66,6 +66,11 @@
Source('se_translating_port_proxy.cc')
Source('page_table.cc')
+ if env['HAVE_DRAMSIM']:
+ SimObject('DRAMSim2.py')
+ Source('dramsim2_wrapper.cc')
+ Source('dramsim2.cc')
+
DebugFlag('BaseBus')
DebugFlag('BusAddrRanges')
DebugFlag('CoherentBus')
@@ -81,6 +86,8 @@
DebugFlag('MemoryAccess')
DebugFlag('PacketQueue')
+DebugFlag("DRAMSim2")
+
DebugFlag('ProtocolTrace')
DebugFlag('RubyCache')
DebugFlag('RubyCacheTrace')
diff -r 58bf21ca88de -r 06a33d872798 src/mem/dramsim2.cc
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/mem/dramsim2.cc Tue Feb 18 05:50:53 2014 -0500
@@ -0,0 +1,410 @@
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ */
+
+#include "DRAMSim2/Callback.h"
+#include "base/callback.hh"
+#include "base/trace.hh"
+#include "debug/DRAMSim2.hh"
+#include "debug/Drain.hh"
+#include "mem/dramsim2.hh"
+#include "sim/system.hh"
+
+DRAMSim2::DRAMSim2(const Params* p) :
+ AbstractMemory(p),
+ port(name() + ".port", *this),
+ wrapper(p->deviceConfigFile, p->systemConfigFile, p->filePath,
+ p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug),
+ retryReq(false), retryResp(false),
+ nbrOutstandingReads(0), nbrOutstandingWrites(0),
+ drainManager(NULL),
+ sendResponseEvent(this), tickEvent(this)
+{
+ DPRINTF(DRAMSim2,
+ "Instantiated DRAMSim2 with clock %d ns and queue size %d\n",
+ wrapper.clockPeriod(), wrapper.queueSize());
+
+ DRAMSim::TransactionCompleteCB* read_cb =
+ new DRAMSim::Callback<DRAMSim2, void, unsigned, uint64_t, uint64_t>(
+ this, &DRAMSim2::readComplete);
+ DRAMSim::TransactionCompleteCB* write_cb =
+ new DRAMSim::Callback<DRAMSim2, void, unsigned, uint64_t, uint64_t>(
+ this, &DRAMSim2::writeComplete);
+ wrapper.setCallbacks(read_cb, write_cb);
+
+ // Register a callback to compensate for the destructor not
+ // being called. The callback prints the DRAMSim2 stats.
+ Callback* cb = new MakeCallback<DRAMSim2Wrapper,
+ &DRAMSim2Wrapper::printStats>(wrapper);
+ registerExitCallback(cb);
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