Hi Nilay, Your last push seems to have broken at least one regression X86, 00.hello, simple-timing-ruby, as it currently segfaults. I suspect it is due to the fact that it tries to forward an address-range change without actually having a pio port connected. Perhaps there are more, this is merely the result of running the quick regressions for a few ISAs.
When looking closer at the code, I am also not sure what about the counting done in recvRangeChange, PioMasterPort in RubyPort.cc. A module may send out many of these updates, so counting does not seem safe to me. Have a look at mem/bus.cc for an example (that is even worse since we also have to deal with the default range). Thanks, Andreas -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
