changeset 24cfe67c0749 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=24cfe67c0749
description:
x86: Setup correct TSL/TR segment attributes on INIT
The TSL/LDT & TR/TSS segments didn't contain valid attributes. This
caused problems when transfering the state into KVM where invalid
state is a no-go. Fixup the attributes with values from AMD's
architecture programmer's manual.
diffstat:
src/arch/x86/faults.cc | 10 ++++++++--
1 files changed, 8 insertions(+), 2 deletions(-)
diffs (27 lines):
diff -r fbfb38d33a0a -r 24cfe67c0749 src/arch/x86/faults.cc
--- a/src/arch/x86/faults.cc Mon Mar 03 14:34:33 2014 +0100
+++ b/src/arch/x86/faults.cc Mon Mar 03 14:44:57 2014 +0100
@@ -245,15 +245,21 @@
tc->setMiscReg(MISCREG_IDTR_BASE, 0);
tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
+ SegAttr tslAttr = 0;
+ tslAttr.present = 1;
+ tslAttr.type = 2; // LDT
tc->setMiscReg(MISCREG_TSL, 0);
tc->setMiscReg(MISCREG_TSL_BASE, 0);
tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
- tc->setMiscReg(MISCREG_TSL_ATTR, 0);
+ tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
+ SegAttr trAttr = 0;
+ trAttr.present = 1;
+ trAttr.type = 3; // Busy 16-bit TSS
tc->setMiscReg(MISCREG_TR, 0);
tc->setMiscReg(MISCREG_TR_BASE, 0);
tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
- tc->setMiscReg(MISCREG_TR_ATTR, 0);
+ tc->setMiscReg(MISCREG_TR_ATTR, trAttr);
// This value should be the family/model/stepping of the processor.
// (page 418). It should be consistent with the value from CPUID, but
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