changeset fd90d9e55e5c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=fd90d9e55e5c
description:
alpha: Small removal of dead comments/code from alpha ISA
Committed by: Nilay Vaish <[email protected]>
diffstat:
src/arch/alpha/isa/mem.isa | 13 -------------
src/cpu/o3/dyn_inst.hh | 7 -------
2 files changed, 0 insertions(+), 20 deletions(-)
diffs (48 lines):
diff -r 580b47334a97 -r fd90d9e55e5c src/arch/alpha/isa/mem.isa
--- a/src/arch/alpha/isa/mem.isa Fri Mar 07 15:56:23 2014 -0500
+++ b/src/arch/alpha/isa/mem.isa Wed Mar 12 07:03:22 2014 -0500
@@ -465,27 +465,14 @@
mem_flags = makeList(mem_flags)
inst_flags = makeList(inst_flags)
- # Some CPU models execute the memory operation as an atomic unit,
- # while others want to separate them into an effective address
- # computation and a memory access operation. As a result, we need
- # to generate three StaticInst objects. Note that the latter two
- # are nested inside the larger "atomic" one.
-
- # Generate InstObjParams for each of the three objects. Note that
- # they differ only in the set of code objects contained (which in
- # turn affects the object's overall operand list).
iop = InstObjParams(name, Name, base_class,
{ 'ea_code':ea_code, 'memacc_code':memacc_code,
'postacc_code':postacc_code },
inst_flags)
- memacc_iop = InstObjParams(name, Name, base_class,
- { 'memacc_code':memacc_code,
'postacc_code':postacc_code },
- inst_flags)
if mem_flags:
mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
iop.constructor += s
- memacc_iop.constructor += s
# select templates
diff -r 580b47334a97 -r fd90d9e55e5c src/cpu/o3/dyn_inst.hh
--- a/src/cpu/o3/dyn_inst.hh Fri Mar 07 15:56:23 2014 -0500
+++ b/src/cpu/o3/dyn_inst.hh Wed Mar 12 07:03:22 2014 -0500
@@ -54,13 +54,6 @@
class Packet;
-/**
- * Mostly implementation & ISA specific AlphaDynInst. As with most
- * other classes in the new CPU model, it is templated on the Impl to
- * allow for passing in of all types, such as the CPU type and the ISA
- * type. The AlphaDynInst serves as the primary interface to the CPU
- * for instructions that are executing.
- */
template <class Impl>
class BaseO3DynInst : public BaseDynInst<Impl>
{
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