Hi Andreas,
I would like to dynamically configure memory in dual, triple redundancy
and copy on write (cow) failure modes. Blacklist failed memory areas and
create memory sandboxes at the interconnect level.
Thanks,
Roger
On Tue, 15 Apr 2014 11:32:15 -0600, Andreas Hansson
<[email protected]> wrote:
Hi Roger,
Could you perhaps shed some light on the bigger picture here. Why do you
want to re-map a slave?
You are right about the fact that ARM and Ruby does not work. In general,
the classic memory system has a broader support. The crossbar model that
is part of the classic memory system can be used to build quite elaborate
interconnect topologies, so hopefully that is enough.
Thanks,
Andreas
On 15/04/2014 18:13, "Roger Smith" <[email protected]> wrote:
I have a newby question. I would like to modify the Interconnect
module(s)
located between the CPU and Slave module to remap the Slave module
address
space. The diagram showing these modules can be seen in the ARM gem5
Tutorial, Bischoff & Hansson, slide 70, titled Ports, Masters, and
Slaves.
I appears there a couple of paths. The first is to modify the AddrMapper
class the second is to modify or write a Ruby script. It seems there are
some issues with Ruby and ARM non-contiguous memory.
Any suggestions on a place to start and route to take?
Thanks,
Roger
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