changeset 2d2c60bda8b2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2d2c60bda8b2
description:
o3: Fix occupancy checks for SMT
A number of calls to isEmpty() and numFreeEntries()
should be thread-specific.
In cpu.cc, the fact that tid is /*commented*/ out is a bug. Say the rob
has instructions from thread 0 (isEmpty() returns false), and none from
thread 1. If we are trying to squash all of thread 1, then
readTailInst(thread 1) will be called because rob->isEmpty() returns
false. The result is end_it is not in the list and the while
statement loops indefinitely back over the cpu's instList.
In iew_impl.hh, all threads are told they have the entire remaining IQ,
when
each thread actually has a certain allocation. The result is extra
stalls at
the iew dispatch stage which the rename stage usually takes care of.
In commit_impl.hh, rob->readHeadInst(thread 1) can be called if the rob
only
contains instructions from thread 0. This returns a dummyInst (which
may work
since we are trying to squash all instructions, but hardly seems like
the right
way to do it).
In rob_impl.hh this fix skips the rest of the function more frequently
and is
more efficient.
Committed by: Nilay Vaish <[email protected]>
diffstat:
src/cpu/o3/commit_impl.hh | 2 +-
src/cpu/o3/cpu.cc | 2 +-
src/cpu/o3/iew_impl.hh | 2 +-
src/cpu/o3/rob_impl.hh | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diffs (48 lines):
diff -r e8608cdddae2 -r 2d2c60bda8b2 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Sat Apr 19 09:00:30 2014 -0500
+++ b/src/cpu/o3/commit_impl.hh Sat Apr 19 09:00:30 2014 -0500
@@ -561,7 +561,7 @@
// then use one older sequence number.
// Hopefully this doesn't mess things up. Basically I want to squash
// all instructions of this thread.
- InstSeqNum squashed_inst = rob->isEmpty() ?
+ InstSeqNum squashed_inst = rob->isEmpty(tid) ?
lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
// All younger instructions will be squashed. Set the sequence
diff -r e8608cdddae2 -r 2d2c60bda8b2 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Sat Apr 19 09:00:30 2014 -0500
+++ b/src/cpu/o3/cpu.cc Sat Apr 19 09:00:30 2014 -0500
@@ -1640,7 +1640,7 @@
if (instList.empty()) {
return;
- } else if (rob.isEmpty(/*tid*/)) {
+ } else if (rob.isEmpty(tid)) {
DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n");
end_it = instList.begin();
rob_empty = true;
diff -r e8608cdddae2 -r 2d2c60bda8b2 src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hh Sat Apr 19 09:00:30 2014 -0500
+++ b/src/cpu/o3/iew_impl.hh Sat Apr 19 09:00:30 2014 -0500
@@ -1598,7 +1598,7 @@
toRename->iewInfo[tid].usedIQ = true;
toRename->iewInfo[tid].freeIQEntries =
- instQueue.numFreeEntries();
+ instQueue.numFreeEntries(tid);
toRename->iewInfo[tid].usedLSQ = true;
toRename->iewInfo[tid].freeLSQEntries =
ldstQueue.numFreeEntries(tid);
diff -r e8608cdddae2 -r 2d2c60bda8b2 src/cpu/o3/rob_impl.hh
--- a/src/cpu/o3/rob_impl.hh Sat Apr 19 09:00:30 2014 -0500
+++ b/src/cpu/o3/rob_impl.hh Sat Apr 19 09:00:30 2014 -0500
@@ -486,7 +486,7 @@
void
ROB<Impl>::squash(InstSeqNum squash_num, ThreadID tid)
{
- if (isEmpty()) {
+ if (isEmpty(tid)) {
DPRINTF(ROB, "Does not need to squash due to being empty "
"[sn:%i]\n",
squash_num);
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