changeset a6402a046e36 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a6402a046e36
description:
arm: Don't use a stack allocated mnemonic
FailUnimplemented passed a stack created mnemonic as a const char *
which
causes some grief when the stack goes away.
diffstat:
src/arch/arm/isa/formats/aarch64.isa | 8 +++++---
src/arch/arm/isa/formats/misc.isa | 29 ++++++++++++++---------------
src/arch/arm/isa/formats/unimp.isa | 20 ++++++++++++++++++--
3 files changed, 37 insertions(+), 20 deletions(-)
diffs (138 lines):
diff -r 790a214be1f4 -r a6402a046e36 src/arch/arm/isa/formats/aarch64.isa
--- a/src/arch/arm/isa/formats/aarch64.isa Wed Apr 23 05:18:18 2014 -0400
+++ b/src/arch/arm/isa/formats/aarch64.isa Wed Apr 23 05:18:20 2014 -0400
@@ -374,9 +374,11 @@
return new WarnUnimplemented(read ? "mrs" : "msr",
machInst, full_mnem);
} else {
- return new FailUnimplemented(csprintf("%s %s",
- read ? "mrs" : "msr",
miscRegName[miscReg]).c_str(),
- machInst);
+ return new FailUnimplemented(read ? "mrs" : "msr",
+ machInst,
+ csprintf("%s %s",
+ read ? "mrs" : "msr",
+ miscRegName[miscReg]));
}
}
break;
diff -r 790a214be1f4 -r a6402a046e36 src/arch/arm/isa/formats/misc.isa
--- a/src/arch/arm/isa/formats/misc.isa Wed Apr 23 05:18:18 2014 -0400
+++ b/src/arch/arm/isa/formats/misc.isa Wed Apr 23 05:18:20 2014 -0400
@@ -139,10 +139,10 @@
case MISCREG_NOP:
return new NopInst(machInst);
case MISCREG_CP14_UNIMPL:
- return new FailUnimplemented(
+ return new FailUnimplemented(isRead ? "mrc unknown" : "mcr
unknown",
+ machInst,
csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s
unknown",
- crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
- machInst);
+ crn, opc1, crm, opc2, isRead ? "read" : "write"));
default:
uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2);
if (isRead) {
@@ -183,10 +183,10 @@
case MISCREG_NOP:
return new NopInst(machInst);
case MISCREG_CP15_UNIMPL:
- return new FailUnimplemented(
+ return new FailUnimplemented(isRead ? "mrc unkown" : "mcr unkown",
+ machInst,
csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s
unknown",
- crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
- machInst);
+ crn, opc1, crm, opc2, isRead ? "read" : "write"));
case MISCREG_DCCMVAC:
return new FlushPipeInst(
isRead ? "mrc dccmvac" : "mcr dccmvac", machInst);
@@ -217,9 +217,9 @@
return new Mrc15(machInst, rt, (IntRegIndex)miscReg, iss);
return new Mcr15(machInst, (IntRegIndex)miscReg, rt, iss);
} else {
- return new FailUnimplemented(csprintf("%s %s",
- isRead ? "mrc" : "mcr", miscRegName[miscReg]).c_str(),
- machInst);
+ return new FailUnimplemented(isRead ? "mrc" : "mcr", machInst,
+ csprintf("%s %s", isRead ? "mrc" : "mcr",
+ miscRegName[miscReg]));
}
}
}
@@ -251,10 +251,9 @@
switch (miscReg) {
case MISCREG_CP15_UNIMPL:
- return new FailUnimplemented(
+ return new FailUnimplemented(isRead ? "mrc" : "mcr", machInst,
csprintf("miscreg crm:%d opc1:%d 64-bit %s unknown",
- crm, opc1, isRead ? "read" : "write").c_str(),
- machInst);
+ crm, opc1, isRead ? "read" : "write"));
default:
if (miscRegInfo[miscReg][MISCREG_WARN_NOT_FAIL]) {
std::string full_mnem = csprintf("%s %s",
@@ -278,9 +277,9 @@
return new Mrrc15(machInst, (IntRegIndex) miscReg, rt2,
rt, iss);
return new Mcrr15(machInst, rt2, rt, (IntRegIndex) miscReg,
iss);
} else {
- return new FailUnimplemented(csprintf("%s %s",
- isRead ? "mrrc" : "mcrr", miscRegName[miscReg]).c_str(),
- machInst);
+ return new FailUnimplemented(isRead ? "mrrc" : "mcrr",
machInst,
+ csprintf("%s %s",
+ isRead ? "mrrc" : "mcrr", miscRegName[miscReg]));
}
}
}
diff -r 790a214be1f4 -r a6402a046e36 src/arch/arm/isa/formats/unimp.isa
--- a/src/arch/arm/isa/formats/unimp.isa Wed Apr 23 05:18:18 2014 -0400
+++ b/src/arch/arm/isa/formats/unimp.isa Wed Apr 23 05:18:20 2014 -0400
@@ -56,6 +56,10 @@
class FailUnimplemented : public ArmStaticInst
{
public:
+ /// Full mnemonic for MRC and MCR instructions including the
+ /// coproc. register name
+ std::string fullMnemonic;
+
/// Constructor
FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst)
: ArmStaticInst(_mnemonic, _machInst, No_OpClass)
@@ -65,6 +69,16 @@
flags[IsNonSpeculative] = true;
}
+ FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst,
+ const std::string& _fullMnemonic)
+ : ArmStaticInst(_mnemonic, _machInst, No_OpClass),
+ fullMnemonic(_fullMnemonic)
+ {
+ // don't call execute() (which panics) if we're on a
+ // speculative path
+ flags[IsNonSpeculative] = true;
+ }
+
%(BasicExecDeclare)s
std::string
@@ -137,14 +151,16 @@
FailUnimplemented::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
- return csprintf("%-10s (unimplemented)", mnemonic);
+ return csprintf("%-10s (unimplemented)",
+ fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
}
std::string
WarnUnimplemented::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
- return csprintf("%-10s (unimplemented)", mnemonic);
+ return csprintf("%-10s (unimplemented)",
+ fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic);
}
std::string
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