> On May 30, 2014, 9:19 a.m., Ahmad Hassan wrote: > > Hi Andreas, > > > > According to the literature, both tCL and tWR should be independent of the > > memory technology because they are buffer constraint timings and they > > reduce the bandwidth (Source: http://dl.acm.org/citation.cfm?id=1555758). > > So tCL and tWR should not be used for distinguishing between read or write > > operation access latency. > > > > Instead, the correct parameters to model read and write access delays in > > DRAM are tRCD and tRP respectively (Source: > > http://dl.acm.org/citation.cfm?id=1555758). But in the current SimpleDRAM > > DDR3 model of GEM5, I changed the following parameters to represent PCM > > read and write latency but I see almost no difference on the CPI. > > > > 1) Increased the tRCD from 13.75ns to '61ns' (PCM is 4.4 times slower than > > dram for read operation) > > 2) Increased tRP from 13.75 to '165ns' (PCM is 12x times slower than dram > > for write operation) > > > > As I see no impact on CPI, does this mean these parameters are not modeled > > correctly in GEM5? However, if I change these parameters in DRAMSim2, then > > I see the difference in average access latency. > > > > Thanks
Hi Ahmad, This is probably better suited for the mailing list. I agree with tCL, but when it comes to tWR I disagree with the statement that it is technology independent. That aside, as you point out, tRCD and tRP are likely to change. I am rather surprised that you see no impact in your experiments. Are you using a recent version of the model (it is not called SimpleDRAM any longer). Also, are you running in timing mode (sorry if this is a stupid question, but I have to check). Finally, are you suggesting you see no difference in the average latency with these changes? - Andreas ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2109/#review5110 ----------------------------------------------------------- On Dec. 6, 2013, 11:09 a.m., Sophiane SENNI wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2109/ > ----------------------------------------------------------- > > (Updated Dec. 6, 2013, 11:09 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > This patch allows specifying different SimpleDRAM latency for read and write > access. (In the code, tCL parameter if for read latency and tCL_write is for > write latency). > > Any feedback is welcomed^^ > > > Diffs > ----- > > src/mem/SimpleDRAM.py 5e8970397ab7 > src/mem/simple_dram.hh 5e8970397ab7 > src/mem/simple_dram.cc 5e8970397ab7 > > Diff: http://reviews.gem5.org/r/2109/diff/ > > > Testing > ------- > > > Thanks, > > Sophiane SENNI > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
