changeset cb2e6950956d in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cb2e6950956d
description:
style: eliminate equality tests with true and false
Using '== true' in a boolean expression is totally redundant,
and using '== false' is pretty verbose (and arguably less
readable in most cases) compared to '!'.
It's somewhat of a pet peeve, perhaps, but I had some time
waiting for some tests to run and decided to clean these up.
Unfortunately, SLICC appears not to have the '!' operator,
so I had to leave the '== false' tests in the SLICC code.
diffstat:
src/arch/mips/tlb.cc | 2 +-
src/arch/power/tlb.cc | 2 +-
src/arch/sparc/tlb.cc | 4 ++--
src/arch/x86/pagetable_walker.cc | 4 ++--
src/base/loader/hex_file.cc | 4 ++--
src/base/match.cc | 2 +-
src/cpu/exetrace.cc | 2 +-
src/cpu/inorder/cpu.cc | 2 +-
src/cpu/inorder/pipeline_stage.cc | 6 +++---
src/cpu/inorder/resources/use_def.cc | 2 +-
src/cpu/o3/commit_impl.hh | 6 +++---
src/cpu/o3/fetch_impl.hh | 4 ++--
src/cpu/o3/iew_impl.hh | 10 +++++-----
src/cpu/o3/inst_queue_impl.hh | 2 +-
src/cpu/o3/lsq_unit_impl.hh | 8 ++++----
src/cpu/o3/rob_impl.hh | 2 +-
src/cpu/ozone/inst_queue_impl.hh | 2 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 6 +++---
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 8 ++++----
src/mem/protocol/MOESI_CMP_token-dir.sm | 2 +-
src/mem/ruby/buffers/MessageBuffer.cc | 2 +-
src/mem/ruby/slicc_interface/NetworkMessage.hh | 4 ++--
src/mem/ruby/system/DMASequencer.cc | 6 +++---
src/mem/slicc/ast/PeekStatementAST.py | 7 +++----
24 files changed, 49 insertions(+), 50 deletions(-)
diffs (truncated from 480 to 300 lines):
diff -r a2bb75a474fd -r cb2e6950956d src/arch/mips/tlb.cc
--- a/src/arch/mips/tlb.cc Sat May 24 21:30:46 2014 -0500
+++ b/src/arch/mips/tlb.cc Sat May 31 18:00:23 2014 -0700
@@ -184,7 +184,7 @@
(pte.D0 << 2) | (pte.V0 <<1) | pte.G),
((pte.PFN1 <<6) | (pte.C1 << 3) |
(pte.D1 << 2) | (pte.V1 <<1) | pte.G));
- if (table[Index].V0 == true || table[Index].V1 == true) {
+ if (table[Index].V0 || table[Index].V1) {
// Previous entry is valid
PageTable::iterator i = lookupTable.find(table[Index].VPN);
lookupTable.erase(i);
diff -r a2bb75a474fd -r cb2e6950956d src/arch/power/tlb.cc
--- a/src/arch/power/tlb.cc Sat May 24 21:30:46 2014 -0500
+++ b/src/arch/power/tlb.cc Sat May 31 18:00:23 2014 -0700
@@ -165,7 +165,7 @@
} else {
// Update TLB
- if (table[Index].V0 == true || table[Index].V1 == true) {
+ if (table[Index].V0 || table[Index].V1) {
// Previous entry is valid
PageTable::iterator i = lookupTable.find(table[Index].VPN);
diff -r a2bb75a474fd -r cb2e6950956d src/arch/sparc/tlb.cc
--- a/src/arch/sparc/tlb.cc Sat May 24 21:30:46 2014 -0500
+++ b/src/arch/sparc/tlb.cc Sat May 31 18:00:23 2014 -0700
@@ -290,7 +290,7 @@
for (int x = 0; x < size; x++) {
if (tlb[x].range.contextId == context_id &&
tlb[x].range.partitionId == partition_id) {
- if (tlb[x].valid == true) {
+ if (tlb[x].valid) {
freeList.push_front(&tlb[x]);
}
tlb[x].valid = false;
@@ -329,7 +329,7 @@
lookupTable.clear();
for (int x = 0; x < size; x++) {
- if (tlb[x].valid == true)
+ if (tlb[x].valid)
freeList.push_back(&tlb[x]);
tlb[x].valid = false;
tlb[x].used = false;
diff -r a2bb75a474fd -r cb2e6950956d src/arch/x86/pagetable_walker.cc
--- a/src/arch/x86/pagetable_walker.cc Sat May 24 21:30:46 2014 -0500
+++ b/src/arch/x86/pagetable_walker.cc Sat May 31 18:00:23 2014 -0700
@@ -233,7 +233,7 @@
Walker::WalkerState::startWalk()
{
Fault fault = NoFault;
- assert(started == false);
+ assert(!started);
started = true;
setupWalk(req->getVaddr());
if (timing) {
@@ -262,7 +262,7 @@
Walker::WalkerState::startFunctional(Addr &addr, unsigned &logBytes)
{
Fault fault = NoFault;
- assert(started == false);
+ assert(!started);
started = true;
setupWalk(addr);
diff -r a2bb75a474fd -r cb2e6950956d src/base/loader/hex_file.cc
--- a/src/base/loader/hex_file.cc Sat May 24 21:30:46 2014 -0500
+++ b/src/base/loader/hex_file.cc Sat May 31 18:00:23 2014 -0700
@@ -104,7 +104,7 @@
} else if (Str[i] == ' ' || Str[i] == '\n') {
if (Number == 0)
return;
- if (Flag == false) {
+ if (!Flag) {
*A = Number;
Number = 0;
Flag = true;
@@ -125,7 +125,7 @@
i++;
}
- if (Flag != true) {
+ if (!Flag) {
*A = 0;
*D = 0;
} else {
diff -r a2bb75a474fd -r cb2e6950956d src/base/match.cc
--- a/src/base/match.cc Sat May 24 21:30:46 2014 -0500
+++ b/src/base/match.cc Sat May 31 18:00:23 2014 -0700
@@ -89,7 +89,7 @@
}
}
- if (match == true)
+ if (match)
return true;
}
diff -r a2bb75a474fd -r cb2e6950956d src/cpu/exetrace.cc
--- a/src/cpu/exetrace.cc Sat May 24 21:30:46 2014 -0500
+++ b/src/cpu/exetrace.cc Sat May 31 18:00:23 2014 -0700
@@ -115,7 +115,7 @@
outs << Enums::OpClassStrings[inst->opClass()] << " : ";
}
- if (Debug::ExecResult && predicate == false) {
+ if (Debug::ExecResult && !predicate) {
outs << "Predicated False";
}
diff -r a2bb75a474fd -r cb2e6950956d src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc Sat May 24 21:30:46 2014 -0500
+++ b/src/cpu/inorder/cpu.cc Sat May 31 18:00:23 2014 -0700
@@ -1763,7 +1763,7 @@
// Clear if Non-Speculative
if (inst->staticInst &&
inst->seqNum == nonSpecSeqNum[tid] &&
- nonSpecInstActive[tid] == true) {
+ nonSpecInstActive[tid]) {
nonSpecInstActive[tid] = false;
}
diff -r a2bb75a474fd -r cb2e6950956d src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc Sat May 24 21:30:46 2014 -0500
+++ b/src/cpu/inorder/pipeline_stage.cc Sat May 31 18:00:23 2014 -0700
@@ -248,19 +248,19 @@
PipelineStage::removeStalls(ThreadID tid)
{
for (int st_num = 0; st_num < NumStages; st_num++) {
- if (stalls[tid].stage[st_num] == true) {
+ if (stalls[tid].stage[st_num]) {
DPRINTF(InOrderStage, "Removing stall from stage %i.\n",
st_num);
stalls[tid].stage[st_num] = false;
}
- if (toPrevStages->stageBlock[st_num][tid] == true) {
+ if (toPrevStages->stageBlock[st_num][tid]) {
DPRINTF(InOrderStage, "Removing pending block from stage %i.\n",
st_num);
toPrevStages->stageBlock[st_num][tid] = false;
}
- if (fromNextStages->stageBlock[st_num][tid] == true) {
+ if (fromNextStages->stageBlock[st_num][tid]) {
DPRINTF(InOrderStage, "Removing pending block from stage %i.\n",
st_num);
fromNextStages->stageBlock[st_num][tid] = false;
diff -r a2bb75a474fd -r cb2e6950956d src/cpu/inorder/resources/use_def.cc
--- a/src/cpu/inorder/resources/use_def.cc Sat May 24 21:30:46 2014 -0500
+++ b/src/cpu/inorder/resources/use_def.cc Sat May 31 18:00:23 2014 -0700
@@ -191,7 +191,7 @@
// If there is a non-speculative instruction
// in the pipeline then stall instructions here
// ---
- if (*nonSpecInstActive[tid] == true && seq_num > *nonSpecSeqNum[tid]) {
+ if (*nonSpecInstActive[tid] && seq_num > *nonSpecSeqNum[tid]) {
DPRINTF(InOrderUseDef, "[tid:%i]: [sn:%i] cannot execute because"
"there is non-speculative instruction [sn:%i] has not "
"graduated.\n", tid, seq_num, *nonSpecSeqNum[tid]);
diff -r a2bb75a474fd -r cb2e6950956d src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Sat May 24 21:30:46 2014 -0500
+++ b/src/cpu/o3/commit_impl.hh Sat May 31 18:00:23 2014 -0700
@@ -843,10 +843,10 @@
// Not sure which one takes priority. I think if we have
// both, that's a bad sign.
- if (trapSquash[tid] == true) {
+ if (trapSquash[tid]) {
assert(!tcSquash[tid]);
squashFromTrap(tid);
- } else if (tcSquash[tid] == true) {
+ } else if (tcSquash[tid]) {
assert(commitStatus[tid] != TrapPending);
squashFromTC(tid);
} else if (commitStatus[tid] == SquashAfterPending) {
@@ -885,7 +885,7 @@
// then use one older sequence number.
InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
- if (fromIEW->includeSquashInst[tid] == true) {
+ if (fromIEW->includeSquashInst[tid]) {
squashed_inst--;
}
diff -r a2bb75a474fd -r cb2e6950956d src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Sat May 24 21:30:46 2014 -0500
+++ b/src/cpu/o3/fetch_impl.hh Sat May 31 18:00:23 2014 -0700
@@ -430,8 +430,8 @@
assert(isDrained());
assert(retryPkt == NULL);
assert(retryTid == InvalidThreadID);
- assert(cacheBlocked == false);
- assert(interruptPending == false);
+ assert(!cacheBlocked);
+ assert(!interruptPending);
for (ThreadID i = 0; i < numThreads; ++i) {
assert(!memReq[i]);
diff -r a2bb75a474fd -r cb2e6950956d src/cpu/o3/iew_impl.hh
--- a/src/cpu/o3/iew_impl.hh Sat May 24 21:30:46 2014 -0500
+++ b/src/cpu/o3/iew_impl.hh Sat May 31 18:00:23 2014 -0700
@@ -487,7 +487,7 @@
DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
"[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
- if (toCommit->squash[tid] == false ||
+ if (!toCommit->squash[tid] ||
inst->seqNum < toCommit->squashedSeqNum[tid]) {
toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum;
@@ -517,7 +517,7 @@
// case the memory violator should take precedence over the branch
// misprediction because it requires the violator itself to be included in
// the squash.
- if (toCommit->squash[tid] == false ||
+ if (!toCommit->squash[tid] ||
inst->seqNum <= toCommit->squashedSeqNum[tid]) {
toCommit->squash[tid] = true;
@@ -538,7 +538,7 @@
{
DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
"PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
- if (toCommit->squash[tid] == false ||
+ if (!toCommit->squash[tid] ||
inst->seqNum < toCommit->squashedSeqNum[tid]) {
toCommit->squash[tid] = true;
@@ -1314,7 +1314,7 @@
}
// If the store had a fault then it may not have a mem req
- if (fault != NoFault || inst->readPredicate() == false ||
+ if (fault != NoFault || !inst->readPredicate() ||
!inst->isStoreConditional()) {
// If the instruction faulted, then we need to send it
along
// to commit without the instruction completing.
@@ -1339,7 +1339,7 @@
// will be replaced and we will lose it.
if (inst->getFault() == NoFault) {
inst->execute();
- if (inst->readPredicate() == false)
+ if (!inst->readPredicate())
inst->forwardOldRegs();
}
diff -r a2bb75a474fd -r cb2e6950956d src/cpu/o3/inst_queue_impl.hh
--- a/src/cpu/o3/inst_queue_impl.hh Sat May 24 21:30:46 2014 -0500
+++ b/src/cpu/o3/inst_queue_impl.hh Sat May 31 18:00:23 2014 -0700
@@ -1262,7 +1262,7 @@
// it be added to the dependency graph.
if (src_reg >= numPhysRegs) {
continue;
- } else if (regScoreboard[src_reg] == false) {
+ } else if (!regScoreboard[src_reg]) {
DPRINTF(IQ, "Instruction PC %s has src reg %i that "
"is being added to the dependency chain.\n",
new_inst->pcState(), src_reg);
diff -r a2bb75a474fd -r cb2e6950956d src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh Sat May 24 21:30:46 2014 -0500
+++ b/src/cpu/o3/lsq_unit_impl.hh Sat May 31 18:00:23 2014 -0700
@@ -612,12 +612,12 @@
// If the instruction faulted or predicated false, then we need to send it
// along to commit without the instruction completing.
- if (load_fault != NoFault || inst->readPredicate() == false) {
+ if (load_fault != NoFault || !inst->readPredicate()) {
// Send this instruction to commit, also make sure iew stage
// realizes there is activity.
// Mark it as executed unless it is an uncached load that
// needs to hit the head of commit.
- if (inst->readPredicate() == false)
+ if (!inst->readPredicate())
inst->forwardOldRegs();
DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n",
inst->seqNum,
@@ -665,7 +665,7 @@
store_fault == NoFault)
return store_fault;
- if (store_inst->readPredicate() == false)
+ if (!store_inst->readPredicate())
store_inst->forwardOldRegs();
if (storeQueue[store_idx].size == 0) {
@@ -673,7 +673,7 @@
store_inst->pcState(), store_inst->seqNum);
return store_fault;
- } else if (store_inst->readPredicate() == false) {
+ } else if (!store_inst->readPredicate()) {
DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n",
store_inst->seqNum);
return store_fault;
diff -r a2bb75a474fd -r cb2e6950956d src/cpu/o3/rob_impl.hh
--- a/src/cpu/o3/rob_impl.hh Sat May 24 21:30:46 2014 -0500
+++ b/src/cpu/o3/rob_impl.hh Sat May 31 18:00:23 2014 -0700
@@ -519,7 +519,7 @@
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