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(Updated June 25, 2014, 3:02 a.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 10243:622ace4c35e7 --------------------------- arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2 the Cortex-A15 has a random replacement policy for its L2 cache. see the Cortex-A15 Technical Reference Manual 1.7 About the L2 memory system. this patch makes the PseudoLRU tags the default for the ARM O3 CPU's L2 cache. Diffs (updated) ----- configs/common/O3_ARM_v7a.py cb4e86c177672fde6be7a409793c944e36353fc0 Diff: http://reviews.gem5.org/r/2173/diff/ Testing ------- Used the memory latency benchmark from LMBench to evaluate the accuracy of gem5's memory system vs. a VExpress board, with this patch the accuracy is much improved. See figure 4a. here: http://web.eecs.umich.edu/~atgutier/papers/ispass_2014.pdf Thanks, Anthony Gutierrez _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
