> On June 30, 2014, 8:34 p.m., Amin Farmahini wrote: > > After applying this patch, the minimum number of float regs should be 160, > > even for ARMv7 ISA. If you set the number of numPhysFloatRegs to lower than > > 160, you get an assertion error from cpu/o3/cpu.cc: > > assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); > > > > The reason is that this patch sets the number of NumFloatRegs based on v8 > > and does not differentiate between v7 and v8 ISAs. See > > src/arch/arm/registers.hh: > > -const int NumFloatArchRegs = 64; > > -const int NumFloatSpecialRegs = 8; > > +const int NumFloatV7ArchRegs = 64; > > +const int NumFloatV8ArchRegs = 128; > > +const int NumFloatSpecialRegs = 32; > > > > -const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; > > +const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; > > > > I think this patch should not change the required number of float regs for > > ARMv7. Am I missing something?
Unfortunately, we need to have a big enough register file for all the FP registers and it's not really possible to differentiate. Long term gem5 will support ARMv8 (32 and 64 bit) only and be backwards compatible for running 32-bit code (pretty much the state it's in now), but it's pretty impossible to properly support to architecture versions simultaneously. - Ali ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2141/#review5169 ----------------------------------------------------------- On Jan. 8, 2014, 8:11 p.m., Ali Saidi wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2141/ > ----------------------------------------------------------- > > (Updated Jan. 8, 2014, 8:11 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10032:5ac3782d2665 > --------------------------- > arm: Add support for ARMv8 (AArch64 & AArch32) > > Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64 > kernel you are restricted to AArch64 user-mode binaries. This will be > addressed > in a later patch. > > Note: Virtualization is only supported in AArch32 mode. This will also be > fixed > in a later patch. > > > Diffs > ----- > > configs/common/FSConfig.py 81d7551dd3be > configs/common/O3_ARM_v7a.py 81d7551dd3be > configs/common/Options.py 81d7551dd3be > configs/common/cpu2000.py 81d7551dd3be > configs/example/fs.py 81d7551dd3be > configs/example/se.py 81d7551dd3be > ext/libelf/elf_common.h 81d7551dd3be > src/arch/arm/ArmISA.py 81d7551dd3be > src/arch/arm/ArmSystem.py 81d7551dd3be > src/arch/arm/ArmTLB.py 81d7551dd3be > src/arch/arm/SConscript 81d7551dd3be > src/arch/arm/decoder.hh 81d7551dd3be > src/arch/arm/decoder.cc 81d7551dd3be > src/arch/arm/faults.hh 81d7551dd3be > src/arch/arm/faults.cc 81d7551dd3be > src/arch/arm/insts/branch64.hh PRE-CREATION > src/arch/arm/insts/branch64.cc PRE-CREATION > src/arch/arm/insts/data64.hh PRE-CREATION > src/arch/arm/insts/data64.cc PRE-CREATION > src/arch/arm/insts/fplib.hh PRE-CREATION > src/arch/arm/insts/fplib.cc PRE-CREATION > src/arch/arm/insts/macromem.hh 81d7551dd3be > src/arch/arm/insts/macromem.cc 81d7551dd3be > src/arch/arm/insts/mem.cc 81d7551dd3be > src/arch/arm/insts/mem64.hh PRE-CREATION > src/arch/arm/insts/mem64.cc PRE-CREATION > src/arch/arm/insts/misc.hh 81d7551dd3be > src/arch/arm/insts/misc.cc 81d7551dd3be > src/arch/arm/insts/misc64.hh PRE-CREATION > src/arch/arm/insts/misc64.cc PRE-CREATION > src/arch/arm/insts/neon64_mem.hh PRE-CREATION > src/arch/arm/insts/pred_inst.hh 81d7551dd3be > src/arch/arm/insts/static_inst.hh 81d7551dd3be > src/arch/arm/insts/static_inst.cc 81d7551dd3be > src/arch/arm/insts/vfp.hh 81d7551dd3be > src/arch/arm/insts/vfp.cc 81d7551dd3be > src/arch/arm/interrupts.hh 81d7551dd3be > src/arch/arm/interrupts.cc 81d7551dd3be > src/arch/arm/intregs.hh 81d7551dd3be > src/arch/arm/isa.hh 81d7551dd3be > src/arch/arm/isa.cc 81d7551dd3be > src/arch/arm/isa/bitfields.isa 81d7551dd3be > src/arch/arm/isa/decoder/aarch64.isa PRE-CREATION > src/arch/arm/isa/decoder/arm.isa 81d7551dd3be > src/arch/arm/isa/decoder/decoder.isa 81d7551dd3be > src/arch/arm/isa/decoder/thumb.isa 81d7551dd3be > src/arch/arm/isa/formats/aarch64.isa PRE-CREATION > src/arch/arm/isa/formats/branch.isa 81d7551dd3be > src/arch/arm/isa/formats/formats.isa 81d7551dd3be > src/arch/arm/isa/formats/fp.isa 81d7551dd3be > src/arch/arm/isa/formats/mem.isa 81d7551dd3be > src/arch/arm/isa/formats/misc.isa 81d7551dd3be > src/arch/arm/isa/formats/neon64.isa PRE-CREATION > src/arch/arm/isa/formats/uncond.isa 81d7551dd3be > src/arch/arm/isa/formats/unimp.isa 81d7551dd3be > src/arch/arm/isa/includes.isa 81d7551dd3be > src/arch/arm/isa/insts/aarch64.isa PRE-CREATION > src/arch/arm/isa/insts/branch.isa 81d7551dd3be > src/arch/arm/isa/insts/branch64.isa PRE-CREATION > src/arch/arm/isa/insts/data.isa 81d7551dd3be > src/arch/arm/isa/insts/data64.isa PRE-CREATION > src/arch/arm/isa/insts/div.isa 81d7551dd3be > src/arch/arm/isa/insts/fp.isa 81d7551dd3be > src/arch/arm/isa/insts/fp64.isa PRE-CREATION > src/arch/arm/isa/insts/insts.isa 81d7551dd3be > src/arch/arm/isa/insts/ldr.isa 81d7551dd3be > src/arch/arm/isa/insts/ldr64.isa PRE-CREATION > src/arch/arm/isa/insts/m5ops.isa 81d7551dd3be > src/arch/arm/isa/insts/macromem.isa 81d7551dd3be > src/arch/arm/isa/insts/mem.isa 81d7551dd3be > src/arch/arm/isa/insts/misc.isa 81d7551dd3be > src/arch/arm/isa/insts/misc64.isa PRE-CREATION > src/arch/arm/isa/insts/neon.isa 81d7551dd3be > src/arch/arm/isa/insts/neon64.isa PRE-CREATION > src/arch/arm/isa/insts/neon64_mem.isa PRE-CREATION > src/arch/arm/isa/insts/str.isa 81d7551dd3be > src/arch/arm/isa/insts/str64.isa PRE-CREATION > src/arch/arm/isa/insts/swap.isa 81d7551dd3be > src/arch/arm/isa/operands.isa 81d7551dd3be > src/arch/arm/isa/templates/basic.isa 81d7551dd3be > src/arch/arm/isa/templates/branch64.isa PRE-CREATION > src/arch/arm/isa/templates/data64.isa PRE-CREATION > src/arch/arm/isa/templates/macromem.isa 81d7551dd3be > src/arch/arm/isa/templates/mem.isa 81d7551dd3be > src/arch/arm/isa/templates/mem64.isa PRE-CREATION > src/arch/arm/isa/templates/misc.isa 81d7551dd3be > src/arch/arm/isa/templates/misc64.isa PRE-CREATION > src/arch/arm/isa/templates/neon.isa 81d7551dd3be > src/arch/arm/isa/templates/neon64.isa PRE-CREATION > src/arch/arm/isa/templates/templates.isa 81d7551dd3be > src/arch/arm/isa/templates/vfp.isa 81d7551dd3be > src/arch/arm/isa/templates/vfp64.isa PRE-CREATION > src/arch/arm/isa_traits.hh 81d7551dd3be > src/arch/arm/linux/linux.hh 81d7551dd3be > src/arch/arm/linux/linux.cc 81d7551dd3be > src/arch/arm/linux/process.hh 81d7551dd3be > src/arch/arm/linux/process.cc 81d7551dd3be > src/arch/arm/linux/system.hh 81d7551dd3be > src/arch/arm/linux/system.cc 81d7551dd3be > src/arch/arm/locked_mem.hh 81d7551dd3be > src/arch/arm/miscregs.hh 81d7551dd3be > src/arch/arm/miscregs.cc 81d7551dd3be > src/arch/arm/nativetrace.cc 81d7551dd3be > src/arch/arm/pagetable.hh 81d7551dd3be > src/arch/arm/process.hh 81d7551dd3be > src/arch/arm/process.cc 81d7551dd3be > src/arch/arm/registers.hh 81d7551dd3be > src/arch/arm/remote_gdb.hh 81d7551dd3be > src/arch/arm/remote_gdb.cc 81d7551dd3be > src/arch/arm/stage2_lookup.hh PRE-CREATION > src/arch/arm/stage2_lookup.cc PRE-CREATION > src/arch/arm/stage2_mmu.hh PRE-CREATION > src/arch/arm/stage2_mmu.cc PRE-CREATION > src/arch/arm/system.hh 81d7551dd3be > src/arch/arm/system.cc 81d7551dd3be > src/arch/arm/table_walker.hh 81d7551dd3be > src/arch/arm/table_walker.cc 81d7551dd3be > src/arch/arm/tlb.hh 81d7551dd3be > src/arch/arm/tlb.cc 81d7551dd3be > src/arch/arm/types.hh 81d7551dd3be > src/arch/arm/utility.hh 81d7551dd3be > src/arch/arm/utility.cc 81d7551dd3be > src/arch/arm/vtophys.cc 81d7551dd3be > src/base/loader/elf_object.hh 81d7551dd3be > src/base/loader/elf_object.cc 81d7551dd3be > src/base/loader/object_file.hh 81d7551dd3be > src/base/loader/object_file.cc 81d7551dd3be > src/cpu/BaseCPU.py 81d7551dd3be > src/dev/arm/RealView.py 81d7551dd3be > src/dev/arm/SConscript 81d7551dd3be > src/dev/arm/generic_timer.hh PRE-CREATION > src/dev/arm/generic_timer.cc PRE-CREATION > src/dev/arm/gic_pl390.cc 81d7551dd3be > src/dev/arm/vgic.hh PRE-CREATION > src/dev/arm/vgic.cc PRE-CREATION > src/sim/System.py 81d7551dd3be > src/sim/process.cc 81d7551dd3be > src/sim/serialize.hh 81d7551dd3be > src/sim/system.hh 81d7551dd3be > src/sim/system.cc 81d7551dd3be > system/arm/aarch64_bootloader/LICENSE.txt PRE-CREATION > system/arm/aarch64_bootloader/boot.S PRE-CREATION > system/arm/aarch64_bootloader/makefile PRE-CREATION > util/cpt_upgrader.py 81d7551dd3be > util/m5/m5op_arm_A64.S PRE-CREATION > > Diff: http://reviews.gem5.org/r/2141/diff/ > > > Testing > ------- > > Existing regression tests run correctly with expected changes. > > AArch64 SE binaries run on SimpleAtomic, SimpleTiming, and O3 CPU models > AArch64 Linux boots on SimpleAtomic, SimpleTiming and O3 models with 1-4 cores > > > Thanks, > > Ali Saidi > > _______________________________________________ gem5-dev mailing list [email protected] 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