I see the value in having Ticked as a separate mix-in so it can apply to non-SimObjects; no argument there. I hadn't thought of the virtual-inheritance-avoidance aspect for SimObjects, but it's a very good rational as well.
Steve On Mon, Jul 21, 2014 at 3:18 AM, Andrew Bardsley via gem5-dev < [email protected]> wrote: > Those objects could derive from TickedObject, yes. Although Minor itself > could be an example of the later class of use if I'd attached the Ticked > interface to MinorCPU rather than the container/abstracting Pipeline object > (not a SimObject). MinorCPU would need to be derived from BaseCPU and > TickedObject but that would have made it inherit from SimObject in two ways > and so required virtual base classes (eek). Migrating BaseCPU to be > derived from TickedObject in the future would, naturally, solve that > problem. > > Quite separately, the former (non SimObject) use case for Ticked could > still remain useful even after that point as, personally, I quite like the > pimpl-ish separation of Pipeline and MinorCPU. > > - Andrew > > -----Original Message----- > From: gem5-dev [mailto:[email protected]] On Behalf Of Steve > Reinhardt via gem5-dev > Sent: 21 July 2014 00:24 > To: Steve Reinhardt; Ali Saidi; Default > Subject: Re: [gem5-dev] Review Request 2279: cpu: `Minor' in-order CPU > model > > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2279/#review5215 > ----------------------------------------------------------- > > Ship it! > > > Looks good, thanks for all the changes. > > One question: in your email you said that Ticked was separate so it could > be "added to objects which are already SimObjects/don't want to be > SimObjects". I get the latter, but in the former case, is there a reason > not to just make those objects derive from TickedObject now? > > - Steve Reinhardt > > > On July 11, 2014, 7:32 a.m., Ali Saidi wrote: > > > > ----------------------------------------------------------- > > This is an automatically generated e-mail. To reply, visit: > > http://reviews.gem5.org/r/2279/ > > ----------------------------------------------------------- > > > > (Updated July 11, 2014, 7:32 a.m.) > > > > > > Review request for Default. > > > > > > Repository: gem5 > > > > > > Description > > ------- > > > > Changeset 10237:5794a56b79c4 > > --------------------------- > > cpu: `Minor' in-order CPU model > > > > This patch contains a new CPU model named `Minor'. Minor models a four > > stage in-order execution pipeline (fetch lines, decompose into > > macroops, decompose macroops into microops, execute). > > > > The model was developed to support the ARM ISA but should be fixable > > to support all the remaining gem5 ISAs. It currently also works for > > Alpha, and regressions are included for ARM and Alpha (including Linux > > boot). > > > > Documentation for the model can be found in src/doc/inside-minor.doxygen > and > > its internal operations can be visualised using the Minorview tool > > utils/minorview.py. > > > > Minor was designed to be fairly simple and not to engage in a lot of > > instruction annotation. As such, it currently has very few gathered > > stats and may lack other gem5 features. > > > > Minor is faster than the o3 model. Sample results: > > > > Benchmark | Stat host_seconds (s) > > ---------------+--------v--------v-------- > > (on ARM, opt) | simple | o3 | minor > > | timing | timing | timing > > ---------------+--------+--------+-------- > > 10.linux-boot | 169 | 1883 | 1075 > > 10.mcf | 117 | 967 | 491 > > 20.parser | 668 | 6315 | 3146 > > 30.eon | 542 | 3413 | 2414 > > 40.perlbmk | 2339 | 20905 | 11532 > > 50.vortex | 122 | 1094 | 588 > > 60.bzip2 | 2045 | 18061 | 9662 > > 70.twolf | 207 | 2736 | 1036 > > > > > > Diffs > > ----- > > > > src/sim/ticked_object.cc PRE-CREATION > > src/sim/ticked_object.hh PRE-CREATION > > src/sim/TickedObject.py PRE-CREATION > > src/sim/SConscript a2bb75a474fd > > src/doc/inside-minor.doxygen PRE-CREATION > > src/cpu/timing_expr.cc PRE-CREATION > > src/cpu/timing_expr.hh PRE-CREATION > > src/cpu/static_inst.hh a2bb75a474fd > > src/cpu/pred/SConscript a2bb75a474fd > > src/cpu/minor/trace.hh PRE-CREATION > > src/cpu/minor/stats.hh PRE-CREATION > > src/cpu/minor/stats.cc PRE-CREATION > > src/cpu/minor/scoreboard.cc PRE-CREATION > > src/cpu/minor/scoreboard.hh PRE-CREATION > > src/cpu/minor/pipeline.cc PRE-CREATION > > src/cpu/minor/pipeline.hh PRE-CREATION > > src/cpu/minor/pipe_data.cc PRE-CREATION > > src/cpu/minor/pipe_data.hh PRE-CREATION > > src/cpu/minor/lsq.cc PRE-CREATION > > src/cpu/minor/lsq.hh PRE-CREATION > > src/cpu/minor/func_unit.cc PRE-CREATION > > src/cpu/minor/func_unit.hh PRE-CREATION > > src/cpu/minor/fetch2.cc PRE-CREATION > > src/cpu/minor/fetch2.hh PRE-CREATION > > src/cpu/minor/fetch1.cc PRE-CREATION > > src/cpu/minor/fetch1.hh PRE-CREATION > > src/cpu/minor/execute.cc PRE-CREATION > > src/cpu/minor/execute.hh PRE-CREATION > > src/cpu/minor/exec_context.hh PRE-CREATION > > src/cpu/minor/dyn_inst.cc PRE-CREATION > > src/cpu/minor/dyn_inst.hh PRE-CREATION > > src/cpu/minor/decode.cc PRE-CREATION > > src/cpu/minor/cpu.cc PRE-CREATION > > src/cpu/minor/decode.hh PRE-CREATION > > src/cpu/minor/cpu.hh PRE-CREATION > > src/cpu/minor/buffers.hh PRE-CREATION > > src/cpu/minor/activity.cc PRE-CREATION > > src/cpu/minor/activity.hh PRE-CREATION > > src/cpu/minor/SConsopts PRE-CREATION > > src/cpu/minor/MinorCPU.py PRE-CREATION > > src/cpu/minor/SConscript PRE-CREATION > > src/cpu/TimingExpr.py PRE-CREATION > > src/cpu/SConscript a2bb75a474fd > > src/base/trace.hh a2bb75a474fd > > configs/common/CpuConfig.py a2bb75a474fd > > build_opts/ARM a2bb75a474fd > > build_opts/ALPHA a2bb75a474fd > > util/minorview.py PRE-CREATION > > util/minorview/__init__.py PRE-CREATION > > util/minorview/blobs.py PRE-CREATION > > util/minorview/colours.py PRE-CREATION > > util/minorview/minor.pic PRE-CREATION > > util/minorview/model.py PRE-CREATION > > util/minorview/parse.py PRE-CREATION > > util/minorview/point.py PRE-CREATION > > util/minorview/view.py PRE-CREATION > > > > Diff: http://reviews.gem5.org/r/2279/diff/ > > > > > > Testing > > ------- > > > > Boots Linux and runs regression tests for ALPHA and ARM. > > > > > > Thanks, > > > > Ali Saidi > > > > > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. > > ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2557590 > ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, > Registered in England & Wales, Company No: 2548782 > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
