changeset f3e9fe1600d6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f3e9fe1600d6
description:
arm: make the PseudoLRU tags the default for the O3_ARM_v7aL2
the Cortex-A15 has a random replacement policy for its L2 cache. see the
Cortex-A15 Technical Reference Manual 1.7 About the L2 memory system.
this
patch makes the PseudoLRU tags the default for the ARM O3 CPU's L2
cache.
diffstat:
configs/common/O3_ARM_v7a.py | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diffs (9 lines):
diff -r dc198e224a85 -r f3e9fe1600d6 configs/common/O3_ARM_v7a.py
--- a/configs/common/O3_ARM_v7a.py Mon Jul 28 01:48:21 2014 -0400
+++ b/configs/common/O3_ARM_v7a.py Mon Jul 28 12:22:00 2014 -0400
@@ -189,4 +189,4 @@
prefetch_on_access = 'true'
# Simple stride prefetcher
prefetcher = StridePrefetcher(degree=8, latency = 1)
-
+ tags = RandomRepl()
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