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(Updated Aug. 1, 2014, 7:04 p.m.) Review request for Default. Repository: gem5 Description (updated) ------- Changeset 10264:c3977836244e --------------------------- sim: stopgap for race-conditions when using multiple EventQueues This patch fixes several race conditions that appear in multi- threaded mode. Currently the decode cache race condition is fixed only for x86, and in a temporary non-optimal fashion. We still need to decide on a more optimal solution for the decode cache and apply it to all the ISAs. Diffs ----- src/arch/x86/decoder.cc c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 src/base/refcnt.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 src/base/trace.cc c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 src/sim/syscall_emul.cc c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 Diff: http://reviews.gem5.org/r/2320/diff/ Testing ------- - Quick regression tests on x86, arm, alpha - Made sure that sparc, power, mips can be built with this patch - Tested using up to 28 EventQueues (28 threads) Thanks, Martin Brown _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
