changeset c7187ee80868 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c7187ee80868
description:
scons: Build the branch predictor for all CPUs
The branch predictor is normally only built when a CPU that uses a
branch predictor is built. The list of CPUs is currently incomplete as
the simple CPUs support branch predictors (for warming, branch stats,
etc). In practice, all CPU models now use branch predictors, so this
changeset removes the CPU model check and replaces it with a check for
the NULL ISA.
diffstat:
src/cpu/pred/SConscript | 23 ++++++++++++-----------
1 files changed, 12 insertions(+), 11 deletions(-)
diffs (31 lines):
diff -r 5b67e1bdf6ad -r c7187ee80868 src/cpu/pred/SConscript
--- a/src/cpu/pred/SConscript Wed Aug 13 06:57:30 2014 -0400
+++ b/src/cpu/pred/SConscript Wed Aug 13 06:57:31 2014 -0400
@@ -30,15 +30,16 @@
Import('*')
-if 'InOrderCPU' in env['CPU_MODELS'] or 'O3CPU' in env['CPU_MODELS'] \
- or 'Minor' in env['CPU_MODELS']:
- SimObject('BranchPredictor.py')
+if env['TARGET_ISA'] == 'null':
+ Return()
- Source('bpred_unit.cc')
- Source('2bit_local.cc')
- Source('btb.cc')
- Source('ras.cc')
- Source('tournament.cc')
- Source ('bi_mode.cc')
- DebugFlag('FreeList')
- DebugFlag('Branch')
+SimObject('BranchPredictor.py')
+
+Source('bpred_unit.cc')
+Source('2bit_local.cc')
+Source('btb.cc')
+Source('ras.cc')
+Source('tournament.cc')
+Source ('bi_mode.cc')
+DebugFlag('FreeList')
+DebugFlag('Branch')
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
