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Review request for Default. Repository: gem5 Description ------- Changeset 10305:2b6478741bf6 --------------------------- arm: Fix v8 neon latency issue for loads/stores Neon memory ops that operate on multiple registers currently have very poor performance because of interleave/deinterleave micro-ops. This patch marks the deinterleave/interleave micro-ops as "No_OpClass" such that they take minumum cycles to execute and are never resource constrained. Additionaly the micro-ops over-read registers. Although one form may need to read up to 20 sources, not all do. This adds in new forms so false dependencies are not modeled. Instructions read their minimum number of sources. Diffs ----- src/arch/arm/insts/macromem.cc 79fde1c67ed8 src/arch/arm/isa/insts/neon64_mem.isa 79fde1c67ed8 Diff: http://reviews.gem5.org/r/2338/diff/ Testing ------- Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
