> On Aug. 16, 2014, 2:13 a.m., Nilay Vaish wrote: > > While I don't understand why there are column bits at the lower end of the > > address, > > I suggest we change the name of the addressing policy to reflect that > > column > > address bits have two subsets. > > Andreas Hansson wrote: > Obviously I need to work on my explanation. Welcome back btw :-) > > In essence, if the system uses a cache line size of 64 bytes, this is the > smallest possible granularity we will interleave things on in the crossbar > (as we cannot go any smaller without cracking a cache line in two). Now, if > the DRAM in question has a burst size of 32 bytes, then a specific controller > is left with a cache line being split across two columns, ranks, banks or > rows. The most sensible choice here is two columns as it is guaranteed to be > a row hit. Does that make more sense? > > I agree with you that it would be nice to capture that there might be > column bits as the LSBs in the name, but it gets pretty tricky as this only > happens if interleaving granularity > DRAM burst size. I could add Coh (Co > high) and Col (Co low) or similar, but I remain unconvinced as to whether > that makes people more or less confused. What do you think?
I think I need some explanation on what address interleaving trying to achieve before carry this discussion further. I am asking this because the dram controller makes use of it. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2325/#review5255 ----------------------------------------------------------- On Aug. 18, 2014, 12:27 p.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2325/ > ----------------------------------------------------------- > > (Updated Aug. 18, 2014, 12:27 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10286:08c7971d5f0a > --------------------------- > mem: Fix address interleaving bug in DRAM controller > > This patch fixes a bug in the DRAM controller address decoding. In > cases where the DRAM burst size was smaller than the interleaving > stripe size (e.g. LPDDR3 x32 with a 64 byte cache line) one address > bit effectively got used as a channel bit when it should have been a > low-order column bit. > > This patch adds a notion of "columns per stripe", and more clearly > deals with the low-order column bits and high-order column bits. The > patch also relaxes the granularity check such that it is possible to > use interleaving granularities other than the cache line size. > > The patch also adds a missing M5_CLASS_VAR_USED to the tCK member as > it is only used in the debug build for now. > > > Diffs > ----- > > src/mem/dram_ctrl.hh 79fde1c67ed8 > src/mem/dram_ctrl.cc 79fde1c67ed8 > > Diff: http://reviews.gem5.org/r/2325/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
