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(Updated Aug. 25, 2014, 9:08 p.m.) Review request for Default. Changes ------- Addressed the opened issues. It turns out refactoring with a base abstract class for the page table is even more complicated than I thought initially, so the class hierarchy is remains the same. Repository: gem5 Description (updated) ------- Changeset 10264:5cf3d07a2e8b --------------------------- Mem: adding a multi-level page table class This patch defines a multi-level page table class that stores the page table in system memory, consistent with ISA specifications. In this way, cpu models that use the actual hardware to execute (e.g. KvmCPU), are able to traverse the page table. Diffs (updated) ----- src/mem/multi_level_page_table.hh PRE-CREATION src/mem/multi_level_page_table.cc PRE-CREATION src/mem/multi_level_page_table_impl.hh PRE-CREATION src/mem/page_table.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 src/mem/page_table.cc c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 src/mem/se_translating_port_proxy.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 src/sim/process.hh c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 src/sim/process.cc c00b5ba43967e7e48a28b7ddc48c9f4afaf2ab76 Diff: http://reviews.gem5.org/r/2312/diff/ Testing ------- Regressions passed. Thanks, Alexandru Dutu _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
