changeset 35738ad3c7c6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=35738ad3c7c6
description:
mem: Fix DRAMSim2 cycle check when restoring from checkpoint
This patch ensures the cycle check is still valid even restoring from
a checkpoint. In this case the DRAMSim2 cycle count is relative to the
startTick rather than 0.
diffstat:
src/mem/dramsim2.cc | 8 +++++---
src/mem/dramsim2.hh | 5 +++++
2 files changed, 10 insertions(+), 3 deletions(-)
diffs (54 lines):
diff -r 9b9ef42122bc -r 35738ad3c7c6 src/mem/dramsim2.cc
--- a/src/mem/dramsim2.cc Tue Aug 26 10:14:32 2014 -0400
+++ b/src/mem/dramsim2.cc Tue Aug 26 10:14:38 2014 -0400
@@ -50,7 +50,7 @@
port(name() + ".port", *this),
wrapper(p->deviceConfigFile, p->systemConfigFile, p->filePath,
p->traceFile, p->range.size() / 1024 / 1024, p->enableDebug),
- retryReq(false), retryResp(false),
+ retryReq(false), retryResp(false), startTick(0),
nbrOutstandingReads(0), nbrOutstandingWrites(0),
drainManager(NULL),
sendResponseEvent(this), tickEvent(this)
@@ -91,6 +91,8 @@
void
DRAMSim2::startup()
{
+ startTick = curTick();
+
// kick off the clock ticks
schedule(tickEvent, clockEdge());
}
@@ -287,7 +289,7 @@
void DRAMSim2::readComplete(unsigned id, uint64_t addr, uint64_t cycle)
{
- assert(cycle == divCeil(curTick(),
+ assert(cycle == divCeil(curTick() - startTick,
wrapper.clockPeriod() * SimClock::Int::ns));
DPRINTF(DRAMSim2, "Read to address %lld complete\n", addr);
@@ -315,7 +317,7 @@
void DRAMSim2::writeComplete(unsigned id, uint64_t addr, uint64_t cycle)
{
- assert(cycle == divCeil(curTick(),
+ assert(cycle == divCeil(curTick() - startTick,
wrapper.clockPeriod() * SimClock::Int::ns));
DPRINTF(DRAMSim2, "Write to address %lld complete\n", addr);
diff -r 9b9ef42122bc -r 35738ad3c7c6 src/mem/dramsim2.hh
--- a/src/mem/dramsim2.hh Tue Aug 26 10:14:32 2014 -0400
+++ b/src/mem/dramsim2.hh Tue Aug 26 10:14:38 2014 -0400
@@ -104,6 +104,11 @@
bool retryResp;
/**
+ * Keep track of when the wrapper is started.
+ */
+ Tick startTick;
+
+ /**
* Keep track of what packets are outstanding per
* address, and do so separately for reads and writes. This is
* done so that we can return the right packet on completion from
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
