changeset bec0c5ffc323 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bec0c5ffc323
description:
mem: adding architectural page table support for SE mode
This patch enables the use of page tables that are stored in system
memory
and respect x86 specification, in SE mode. It defines an architectural
page table for x86 as a MultiLevelPageTable class and puts a placeholder
class for other ISAs page tables, giving the possibility for future
implementation.
diffstat:
src/arch/alpha/process.hh | 3 +
src/arch/arm/process.hh | 3 +
src/arch/mips/process.hh | 3 +
src/arch/power/process.hh | 3 +
src/arch/sparc/process.hh | 3 +
src/arch/x86/pagetable.hh | 85 ++++++++++++++++++++++++++++++++++++++++
src/arch/x86/pagetable_walker.cc | 17 --------
src/arch/x86/process.hh | 9 ++++
src/arch/x86/system.hh | 14 ++++++
src/mem/SConscript | 2 +
src/sim/Process.py | 2 +
src/sim/process.cc | 5 +-
src/sim/process.hh | 2 +
13 files changed, 133 insertions(+), 18 deletions(-)
diffs (truncated from 305 to 300 lines):
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/alpha/process.hh
--- a/src/arch/alpha/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/alpha/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -55,4 +55,7 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __ARCH_ALPHA_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/arm/process.hh
--- a/src/arch/arm/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/arm/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -98,5 +98,8 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __ARM_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/mips/process.hh
--- a/src/arch/mips/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/mips/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -59,5 +59,8 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __MIPS_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/power/process.hh
--- a/src/arch/power/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/power/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -58,5 +58,8 @@
void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __POWER_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/sparc/process.hh
--- a/src/arch/sparc/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/sparc/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -131,4 +131,7 @@
void setSyscallArg(ThreadContext *tc, int i, SparcISA::IntReg val);
};
+/* No architectural page table defined for this ISA */
+typedef NoArchPageTable ArchPageTable;
+
#endif // __SPARC_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/x86/pagetable.hh
--- a/src/arch/x86/pagetable.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/x86/pagetable.hh Thu Aug 28 10:11:44 2014 -0500
@@ -1,4 +1,5 @@
/*
+ * Copyright (c) 2014 Advanced Micro Devices, Inc.
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
@@ -42,11 +43,15 @@
#include <iostream>
#include <string>
+#include <vector>
#include "base/bitunion.hh"
#include "base/misc.hh"
#include "base/types.hh"
#include "base/trie.hh"
+#include "cpu/thread_context.hh"
+#include "arch/x86/system.hh"
+#include "debug/MMU.hh"
class Checkpoint;
@@ -73,6 +78,25 @@
Bitfield<31, 22> norml2;
EndBitUnion(VAddr)
+ // Unfortunately, the placement of the base field in a page table entry is
+ // very erratic and would make a mess here. It might be moved here at some
+ // point in the future.
+ BitUnion64(PageTableEntry)
+ Bitfield<63> nx;
+ Bitfield<51, 12> base;
+ Bitfield<11, 9> avl;
+ Bitfield<8> g;
+ Bitfield<7> ps;
+ Bitfield<6> d;
+ Bitfield<5> a;
+ Bitfield<4> pcd;
+ Bitfield<3> pwt;
+ Bitfield<2> u;
+ Bitfield<1> w;
+ Bitfield<0> p;
+ EndBitUnion(PageTableEntry)
+
+
struct TlbEntry
{
// The base of the physical page.
@@ -127,6 +151,67 @@
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string §ion);
};
+
+ /** The size of each level of the page table expressed in base 2
+ * logarithmic values
+ */
+ const std::vector<uint8_t> PageTableLayout = {9, 9, 9, 9};
+
+ enum PTEField{
+ PTE_NotPresent = 0,
+ PTE_Present,
+ PTE_ReadOnly = 0,
+ PTE_ReadWrite,
+ PTE_Supervisor = 0,
+ PTE_UserSupervisor,
+ };
+
+ /** Page table operations specific to x86 ISA.
+ * Indended to be used as parameter of MultiLevelPageTable.
+ */
+ class PageTableOps
+ {
+ public:
+ void setPTEFields(PageTableEntry& PTE,
+ uint64_t present = PTE_Present,
+ uint64_t read_write = PTE_ReadWrite,
+ uint64_t user_supervisor = PTE_UserSupervisor)
+ {
+ PTE.p = present;
+ PTE.w = read_write;
+ PTE.u = user_supervisor;// both user and supervisor access allowed
+ }
+
+ /** returns the physical memory address of the page table */
+ Addr getBasePtr(ThreadContext* tc)
+ {
+ CR3 cr3 = pageTablePhysAddr;
+ DPRINTF(MMU, "CR3: %d\n", cr3);
+ return cr3.longPdtb;
+ }
+
+ /** returns the page number out of a page table entry */
+ Addr getPnum(PageTableEntry PTE)
+ {
+ return PTE.base;
+ }
+
+ /** sets the page number in a page table entry */
+ void setPnum(PageTableEntry& PTE, Addr paddr)
+ {
+ PTE.base = paddr;
+ }
+
+ /** returns the offsets to index in every level of a page
+ * table, contained in a virtual address
+ */
+ std::vector<uint64_t> getOffsets(Addr vaddr)
+ {
+ X86ISA::VAddr addr(vaddr);
+ return {addr.longl1, addr.longl2, addr.longl3, addr.longl4};
+ }
+ };
+
}
#endif
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/x86/pagetable_walker.cc
--- a/src/arch/x86/pagetable_walker.cc Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/x86/pagetable_walker.cc Thu Aug 28 10:11:44 2014 -0500
@@ -63,23 +63,6 @@
namespace X86ISA {
-// Unfortunately, the placement of the base field in a page table entry is
-// very erratic and would make a mess here. It might be moved here at some
-// point in the future.
-BitUnion64(PageTableEntry)
- Bitfield<63> nx;
- Bitfield<11, 9> avl;
- Bitfield<8> g;
- Bitfield<7> ps;
- Bitfield<6> d;
- Bitfield<5> a;
- Bitfield<4> pcd;
- Bitfield<3> pwt;
- Bitfield<2> u;
- Bitfield<1> w;
- Bitfield<0> p;
-EndBitUnion(PageTableEntry)
-
Fault
Walker::start(ThreadContext * _tc, BaseTLB::Translation *_translation,
RequestPtr _req, BaseTLB::Mode _mode)
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/x86/process.hh
--- a/src/arch/x86/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/x86/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -44,6 +44,7 @@
#include <vector>
#include "sim/process.hh"
+#include "mem/multi_level_page_table.hh"
class SyscallDesc;
@@ -133,6 +134,14 @@
X86ISA::IntReg getSyscallArg(ThreadContext *tc, int &i, int width);
void setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val);
};
+
+ /**
+ * Declaration of architectural page table for x86.
+ *
+ * These page tables are stored in system memory and respect x86
specification.
+ */
+ typedef MultiLevelPageTable<PageTableOps> ArchPageTable;
+
}
#endif // __ARCH_X86_PROCESS_HH__
diff -r 77af86f37337 -r bec0c5ffc323 src/arch/x86/system.hh
--- a/src/arch/x86/system.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/arch/x86/system.hh Thu Aug 28 10:11:44 2014 -0500
@@ -61,6 +61,20 @@
class FloatingPointer;
class ConfigTable;
}
+
+ /* memory mappings for KVMCpu in SE mode */
+ const uint64_t syscallCodeVirtAddr = 0xffff800000000000;
+ const uint64_t syscallCodePhysAddr = 0x60000;
+ const uint64_t GDTVirtAddr = 0xffff800000001000;
+ const uint64_t GDTPhysAddr = 0x61000;
+ const uint64_t IDTVirtAddr = 0xffff800000002000;
+ const uint64_t IDTPhysAddr = 0x62000;
+ const uint64_t TSSVirtAddr = 0xffff800000003000;
+ const uint64_t TSSPhysAddr = 0x63000;
+ const uint64_t ISTVirtAddr = 0xffff800000004000;
+ const uint64_t ISTPhysAddr = 0x64000;
+
+ const uint64_t pageTablePhysAddr = 0x70000;
}
class X86System : public System
diff -r 77af86f37337 -r bec0c5ffc323 src/mem/SConscript
--- a/src/mem/SConscript Tue Apr 01 12:18:12 2014 -0500
+++ b/src/mem/SConscript Thu Aug 28 10:11:44 2014 -0500
@@ -65,6 +65,8 @@
Source('fs_translating_port_proxy.cc')
Source('se_translating_port_proxy.cc')
Source('page_table.cc')
+if env['TARGET_ISA'] == 'x86':
+ Source('multi_level_page_table.cc')
if env['HAVE_DRAMSIM']:
SimObject('DRAMSim2.py')
diff -r 77af86f37337 -r bec0c5ffc323 src/sim/Process.py
--- a/src/sim/Process.py Tue Apr 01 12:18:12 2014 -0500
+++ b/src/sim/Process.py Thu Aug 28 10:11:44 2014 -0500
@@ -38,6 +38,8 @@
output = Param.String('cout', 'filename for stdout')
errout = Param.String('cerr', 'filename for stderr')
system = Param.System(Parent.any, "system process will run on")
+ useArchPT = Param.Bool('false', 'maintain an in-memory version of the page\
+ table in an architecture-specific format')
max_stack_size = Param.MemorySize('64MB', 'maximum size of the stack')
@classmethod
diff -r 77af86f37337 -r bec0c5ffc323 src/sim/process.cc
--- a/src/sim/process.cc Tue Apr 01 12:18:12 2014 -0500
+++ b/src/sim/process.cc Thu Aug 28 10:11:44 2014 -0500
@@ -106,7 +106,10 @@
: SimObject(params), system(params->system),
max_stack_size(params->max_stack_size),
M5_pid(system->allocatePID()),
- pTable(new FuncPageTable(name(), M5_pid)),
+ useArchPT(params->useArchPT),
+ pTable(useArchPT ?
+ static_cast<PageTableBase *>(new ArchPageTable(name(), M5_pid,
system)) :
+ static_cast<PageTableBase *>(new FuncPageTable(name(), M5_pid)) ),
initVirtMem(system->getSystemPort(), this,
SETranslatingPortProxy::Always)
{
diff -r 77af86f37337 -r bec0c5ffc323 src/sim/process.hh
--- a/src/sim/process.hh Tue Apr 01 12:18:12 2014 -0500
+++ b/src/sim/process.hh Thu Aug 28 10:11:44 2014 -0500
@@ -125,6 +125,8 @@
//separated.
uint64_t M5_pid;
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