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Ship it! very much look forward to this. doFastWrites is always set to true. Does it make sense to add doFastWrites to the list of parameters in BaseCache.py? - Amin Farmahini On Aug. 27, 2014, 4:16 p.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2341/ > ----------------------------------------------------------- > > (Updated Aug. 27, 2014, 4:16 p.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10323:33baf6c26f18 > --------------------------- > mem: write streaming support via WriteInvalidate promotion > > Support full-block writes directly rather than requiring RMW: > * a cache line is allocated in the cache upon receipt of a > WriteInvalidateReq, not the WriteInvalidateResp. > * only top-level caches allocate the line; the others just pass > the request along and invalidate as necessary. > * to close a timing window between the *Req and the *Resp, a new > metadata bit tracks whether another cache has read a copy of > the new line before the writeback to memory. > > > Diffs > ----- > > src/mem/cache/base.hh 2a1d75864ad2 > src/mem/cache/base.cc 2a1d75864ad2 > src/mem/cache/blk.hh 2a1d75864ad2 > src/mem/cache/cache.hh 2a1d75864ad2 > src/mem/cache/cache_impl.hh 2a1d75864ad2 > src/mem/packet.hh 2a1d75864ad2 > src/mem/packet.cc 2a1d75864ad2 > > Diff: http://reviews.gem5.org/r/2341/diff/ > > > Testing > ------- > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
