changeset ad9c042dce54 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ad9c042dce54
description:
ruby: message buffers: significant changes
This patch is the final patch in a series of patches. The aim of the
series
is to make ruby more configurable than it was. More specifically, the
connections between controllers are not at all possible (unless one is
ready
to make significant changes to the coherence protocol). Moreover the
buffers
themselves are magically connected to the network inside the slicc code.
These connections are not part of the configuration file.
This patch makes changes so that these connections will now be made in
the
python configuration files associated with the protocols. This requires
each state machine to expose the message buffers it uses for input and
output.
So, the patch makes these buffers configurable members of the machines.
The patch drops the slicc code that usd to connect these buffers to the
network. Now these buffers are exposed to the python configuration
system
as Master and Slave ports. In the configuration files, any master port
can be connected any slave port. The file pyobject.cc has been
modified to
take care of allocating the actual message buffer. This is inline with
how
other port connections work.
diffstat:
configs/ruby/MESI_Three_Level.py | 28 +-
configs/ruby/MESI_Two_Level.py | 35 +-
configs/ruby/MI_example.py | 25 +-
configs/ruby/MOESI_CMP_directory.py | 29 +-
configs/ruby/MOESI_CMP_token.py | 35 +-
configs/ruby/MOESI_hammer.py | 31 +-
configs/ruby/Network_test.py | 14 +-
configs/ruby/Ruby.py | 56 +-
src/mem/protocol/MESI_Three_Level-L0cache.sm | 13 +-
src/mem/protocol/MESI_Three_Level-L1cache.sm | 42 +-
src/mem/protocol/MESI_Two_Level-L1cache.sm | 39 +-
src/mem/protocol/MESI_Two_Level-L2cache.sm | 27 +-
src/mem/protocol/MESI_Two_Level-dir.sm | 22 +-
src/mem/protocol/MESI_Two_Level-dma.sm | 15 +-
src/mem/protocol/MI_example-cache.sm | 29 +-
src/mem/protocol/MI_example-dir.sm | 26 +-
src/mem/protocol/MI_example-dma.sm | 19 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 35 +-
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 23 +-
src/mem/protocol/MOESI_CMP_directory-dir.sm | 21 +-
src/mem/protocol/MOESI_CMP_directory-dma.sm | 26 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 42 +-
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 51 +-
src/mem/protocol/MOESI_CMP_token-dir.sm | 38 +-
src/mem/protocol/MOESI_CMP_token-dma.sm | 15 +-
src/mem/protocol/MOESI_hammer-cache.sm | 41 +-
src/mem/protocol/MOESI_hammer-dir.sm | 51 +-
src/mem/protocol/MOESI_hammer-dma.sm | 23 +-
src/mem/protocol/Network_test-cache.sm | 18 +-
src/mem/protocol/Network_test-dir.sm | 12 +-
src/mem/ruby/network/Network.cc | 23 +-
src/mem/ruby/network/Network.hh | 13 +-
src/mem/ruby/network/Network.py | 4 +-
src/mem/ruby/network/garnet/BaseGarnetNetwork.cc | 16 +-
src/mem/ruby/network/garnet/BaseGarnetNetwork.hh | 11 +-
src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc | 36 +-
src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh | 9 +-
src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc | 44 +-
src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh | 8 +-
src/mem/ruby/network/garnet/flexible-pipeline/Router.cc | 2 +-
src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc | 11 -
src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh | 1 -
src/mem/ruby/network/simple/PerfectSwitch.cc | 34 +-
src/mem/ruby/network/simple/PerfectSwitch.hh | 10 +-
src/mem/ruby/network/simple/SimpleNetwork.cc | 34 +-
src/mem/ruby/network/simple/SimpleNetwork.hh | 9 +-
src/mem/ruby/network/simple/Switch.cc | 26 +-
src/mem/ruby/network/simple/Switch.hh | 11 +-
src/mem/ruby/network/simple/Throttle.cc | 157 +++---
src/mem/ruby/network/simple/Throttle.hh | 15 +-
src/mem/ruby/slicc_interface/AbstractController.cc | 7 -
src/mem/ruby/slicc_interface/AbstractController.hh | 19 +-
src/mem/slicc/symbols/StateMachine.py | 210
+++++----
src/python/swig/pyobject.cc | 22 +
54 files changed, 941 insertions(+), 672 deletions(-)
diffs (truncated from 2850 to 300 lines):
diff -r 61c7f1d06575 -r ad9c042dce54 configs/ruby/MESI_Three_Level.py
--- a/configs/ruby/MESI_Three_Level.py Mon Sep 01 16:55:46 2014 -0500
+++ b/configs/ruby/MESI_Three_Level.py Mon Sep 01 16:55:47 2014 -0500
@@ -129,7 +129,19 @@
cpu_sequencers.append(cpu_seq)
l0_cntrl_nodes.append(l0_cntrl)
l1_cntrl_nodes.append(l1_cntrl)
- l0_cntrl.peer = l1_cntrl
+
+ # Connect the L0 and L1 controllers
+ l0_cntrl.bufferToL1 = l1_cntrl.bufferFromL0
+ l0_cntrl.bufferFromL1 = l1_cntrl.bufferToL0
+
+ # Connect the L1 controllers and the network
+ l1_cntrl.requestToL2 = ruby_system.network.slave
+ l1_cntrl.responseToL2 = ruby_system.network.slave
+ l1_cntrl.unblockToL2 = ruby_system.network.slave
+
+ l1_cntrl.requestFromL2 = ruby_system.network.master
+ l1_cntrl.responseFromL2 = ruby_system.network.master
+
for j in xrange(num_l2caches_per_cluster):
l2_cache = L2Cache(size = options.l2_size,
@@ -146,6 +158,15 @@
i * num_l2caches_per_cluster + j))
l2_cntrl_nodes.append(l2_cntrl)
+ # Connect the L2 controllers and the network
+ l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.responseFromL2Cache = ruby_system.network.slave
+
+ l2_cntrl.unblockToL2Cache = ruby_system.network.master
+ l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
+ l2_cntrl.responseToL2Cache = ruby_system.network.master
+
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
@@ -183,6 +204,11 @@
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ # Connect the directory controllers and the network
+ dir_cntrl.requestToDir = ruby_system.network.master
+ dir_cntrl.responseToDir = ruby_system.network.master
+ dir_cntrl.responseFromDir = ruby_system.network.slave
+
for i, dma_port in enumerate(dma_ports):
#
# Create the Ruby objects associated with the dma controller
diff -r 61c7f1d06575 -r ad9c042dce54 configs/ruby/MESI_Two_Level.py
--- a/configs/ruby/MESI_Two_Level.py Mon Sep 01 16:55:46 2014 -0500
+++ b/configs/ruby/MESI_Two_Level.py Mon Sep 01 16:55:47 2014 -0500
@@ -108,12 +108,19 @@
l1_cntrl.sequencer = cpu_seq
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
- #
# Add controllers and sequencers to the appropriate lists
- #
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ # Connect the L1 controllers and the network
+ l1_cntrl.requestFromL1Cache = ruby_system.network.slave
+ l1_cntrl.responseFromL1Cache = ruby_system.network.slave
+ l1_cntrl.unblockFromL1Cache = ruby_system.network.slave
+
+ l1_cntrl.requestToL1Cache = ruby_system.network.master
+ l1_cntrl.responseToL1Cache = ruby_system.network.master
+
+
l2_index_start = block_size_bits + l2_bits
for i in xrange(options.num_l2caches):
@@ -132,10 +139,21 @@
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
+ # Connect the L2 controllers and the network
+ l2_cntrl.DirRequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.responseFromL2Cache = ruby_system.network.slave
+
+ l2_cntrl.unblockToL2Cache = ruby_system.network.master
+ l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
+ l2_cntrl.responseToL2Cache = ruby_system.network.master
+
+
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
+
# Run each of the ruby memory controllers at a ratio of the frequency of
# the ruby system
# clk_divider value is a fix to pass regression.
@@ -169,10 +187,14 @@
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ # Connect the directory controllers and the network
+ dir_cntrl.requestToDir = ruby_system.network.master
+ dir_cntrl.responseToDir = ruby_system.network.master
+ dir_cntrl.responseFromDir = ruby_system.network.slave
+
+
for i, dma_port in enumerate(dma_ports):
- #
# Create the Ruby objects associated with the dma controller
- #
dma_seq = DMASequencer(version = i,
ruby_system = ruby_system)
@@ -185,6 +207,11 @@
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
+ # Connect the dma controller to the network
+ dma_cntrl.responseFromDir = ruby_system.network.master
+ dma_cntrl.requestToDir = ruby_system.network.slave
+
+
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
dir_cntrl_nodes + \
diff -r 61c7f1d06575 -r ad9c042dce54 configs/ruby/MI_example.py
--- a/configs/ruby/MI_example.py Mon Sep 01 16:55:46 2014 -0500
+++ b/configs/ruby/MI_example.py Mon Sep 01 16:55:47 2014 -0500
@@ -94,12 +94,17 @@
l1_cntrl.sequencer = cpu_seq
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
- #
# Add controllers and sequencers to the appropriate lists
- #
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ # Connect the L1 controllers and the network
+ l1_cntrl.requestFromCache = ruby_system.network.slave
+ l1_cntrl.responseFromCache = ruby_system.network.slave
+ l1_cntrl.forwardToCache = ruby_system.network.master
+ l1_cntrl.responseToCache = ruby_system.network.master
+
+
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
@@ -139,6 +144,15 @@
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ # Connect the directory controllers and the network
+ dir_cntrl.requestToDir = ruby_system.network.master
+ dir_cntrl.dmaRequestToDir = ruby_system.network.master
+
+ dir_cntrl.responseFromDir = ruby_system.network.slave
+ dir_cntrl.dmaResponseFromDir = ruby_system.network.slave
+ dir_cntrl.forwardFromDir = ruby_system.network.slave
+
+
for i, dma_port in enumerate(dma_ports):
#
# Create the Ruby objects associated with the dma controller
@@ -155,8 +169,11 @@
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
+ # Connect the directory controllers and the network
+ dma_cntrl.requestToDir = ruby_system.network.master
+ dma_cntrl.responseFromDir = ruby_system.network.slave
+
+
all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
-
topology = create_topology(all_cntrls, options)
-
return (cpu_sequencers, dir_cntrl_nodes, topology)
diff -r 61c7f1d06575 -r ad9c042dce54 configs/ruby/MOESI_CMP_directory.py
--- a/configs/ruby/MOESI_CMP_directory.py Mon Sep 01 16:55:46 2014 -0500
+++ b/configs/ruby/MOESI_CMP_directory.py Mon Sep 01 16:55:47 2014 -0500
@@ -104,12 +104,17 @@
l1_cntrl.sequencer = cpu_seq
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
- #
# Add controllers and sequencers to the appropriate lists
- #
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ # Connect the L1 controllers and the network
+ l1_cntrl.requestFromL1Cache = ruby_system.network.slave
+ l1_cntrl.responseFromL1Cache = ruby_system.network.slave
+ l1_cntrl.requestToL1Cache = ruby_system.network.master
+ l1_cntrl.responseToL1Cache = ruby_system.network.master
+
+
l2_index_start = block_size_bits + l2_bits
for i in xrange(options.num_l2caches):
@@ -128,10 +133,21 @@
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
+ # Connect the L2 controllers and the network
+ l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.responseFromL2Cache = ruby_system.network.slave
+
+ l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master
+ l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
+ l2_cntrl.responseToL2Cache = ruby_system.network.master
+
+
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
+
# Run each of the ruby memory controllers at a ratio of the frequency of
# the ruby system.
# clk_divider value is a fix to pass regression.
@@ -164,6 +180,13 @@
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
+ # Connect the directory controllers and the network
+ dir_cntrl.requestToDir = ruby_system.network.master
+ dir_cntrl.responseToDir = ruby_system.network.master
+ dir_cntrl.responseFromDir = ruby_system.network.slave
+ dir_cntrl.forwardFromDir = ruby_system.network.slave
+
+
for i, dma_port in enumerate(dma_ports):
#
# Create the Ruby objects associated with the dma controller
@@ -180,11 +203,11 @@
exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
+
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
dir_cntrl_nodes + \
dma_cntrl_nodes
topology = create_topology(all_cntrls, options)
-
return (cpu_sequencers, dir_cntrl_nodes, topology)
diff -r 61c7f1d06575 -r ad9c042dce54 configs/ruby/MOESI_CMP_token.py
--- a/configs/ruby/MOESI_CMP_token.py Mon Sep 01 16:55:46 2014 -0500
+++ b/configs/ruby/MOESI_CMP_token.py Mon Sep 01 16:55:47 2014 -0500
@@ -124,12 +124,20 @@
l1_cntrl.sequencer = cpu_seq
exec("ruby_system.l1_cntrl%d = l1_cntrl" % i)
- #
# Add controllers and sequencers to the appropriate lists
- #
cpu_sequencers.append(cpu_seq)
l1_cntrl_nodes.append(l1_cntrl)
+ # Connect the L1 controllers and the network
+ l1_cntrl.requestFromL1Cache = ruby_system.network.slave
+ l1_cntrl.responseFromL1Cache = ruby_system.network.slave
+ l1_cntrl.persistentFromL1Cache = ruby_system.network.slave
+
+ l1_cntrl.requestToL1Cache = ruby_system.network.master
+ l1_cntrl.responseToL1Cache = ruby_system.network.master
+ l1_cntrl.persistentToL1Cache = ruby_system.network.master
+
+
l2_index_start = block_size_bits + l2_bits
for i in xrange(options.num_l2caches):
@@ -149,6 +157,17 @@
exec("ruby_system.l2_cntrl%d = l2_cntrl" % i)
l2_cntrl_nodes.append(l2_cntrl)
+ # Connect the L2 controllers and the network
+ l2_cntrl.GlobalRequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.L1RequestFromL2Cache = ruby_system.network.slave
+ l2_cntrl.responseFromL2Cache = ruby_system.network.slave
+
+ l2_cntrl.GlobalRequestToL2Cache = ruby_system.network.master
+ l2_cntrl.L1RequestToL2Cache = ruby_system.network.master
+ l2_cntrl.responseToL2Cache = ruby_system.network.master
+ l2_cntrl.persistentToL2Cache = ruby_system.network.master
+
+
phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges))
assert(phys_mem_size % options.num_dirs == 0)
mem_module_size = phys_mem_size / options.num_dirs
@@ -186,6 +205,18 @@
exec("ruby_system.dir_cntrl%d = dir_cntrl" % i)
dir_cntrl_nodes.append(dir_cntrl)
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