changeset 98771a936b61 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=98771a936b61
description:
arch: Cleanup unused ISA traits constants
This patch prunes unused values, and also unifies how the values are
defined (not using an enum for ALPHA), aligning the use of int vs Addr
etc.
The patch also removes the duplication of PageBytes/PageShift and
VMPageSize/LogVMPageSize. For all ISAs the two pairs had identical
values and the latter has been removed.
diffstat:
src/arch/alpha/isa_traits.hh | 14 +-------------
src/arch/alpha/process.cc | 6 +++---
src/arch/arm/isa_traits.hh | 11 -----------
src/arch/arm/process.cc | 10 +++++-----
src/arch/arm/utility.cc | 1 +
src/arch/mips/isa_traits.hh | 10 ----------
src/arch/mips/process.cc | 6 +++---
src/arch/null/isa_traits.hh | 3 ---
src/arch/power/isa_traits.hh | 3 ---
src/arch/power/process.cc | 6 +++---
src/arch/sparc/isa_traits.hh | 14 ++------------
src/arch/sparc/process.cc | 8 ++++----
src/arch/x86/isa_traits.hh | 10 ++--------
src/arch/x86/process.cc | 14 +++++++-------
src/kern/tru64/tru64.hh | 8 ++++----
src/mem/cache/prefetch/base.cc | 2 +-
src/mem/multi_level_page_table_impl.hh | 24 ++++++++++++------------
src/mem/page_table.hh | 6 +++---
src/mem/ruby/common/Address.cc | 2 +-
src/mem/se_translating_port_proxy.cc | 14 +++++++-------
src/sim/process.cc | 4 ++--
src/sim/syscall_emul.cc | 12 ++++++------
src/sim/syscall_emul.hh | 10 +++++-----
src/sim/system.cc | 6 +++---
24 files changed, 75 insertions(+), 129 deletions(-)
diffs (truncated from 730 to 300 lines):
diff -r 19f5df7ac6a1 -r 98771a936b61 src/arch/alpha/isa_traits.hh
--- a/src/arch/alpha/isa_traits.hh Wed Sep 03 07:42:20 2014 -0400
+++ b/src/arch/alpha/isa_traits.hh Wed Sep 03 07:42:21 2014 -0400
@@ -109,19 +109,7 @@
mode_number // number of modes
};
-// Constants Related to the number of registers
-
-enum {
- LogVMPageSize = 13, // 8K bytes
- VMPageSize = (1 << LogVMPageSize),
-
- BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
-
- MachineBytes = 8,
- WordBytes = 4,
- HalfwordBytes = 2,
- ByteBytes = 1
-};
+const int MachineBytes = 8;
// return a no-op instruction... used for instruction fetch faults
// Alpha UNOP (ldq_u r31,0(r0))
diff -r 19f5df7ac6a1 -r 98771a936b61 src/arch/alpha/process.cc
--- a/src/arch/alpha/process.cc Wed Sep 03 07:42:20 2014 -0400
+++ b/src/arch/alpha/process.cc Wed Sep 03 07:42:21 2014 -0400
@@ -49,7 +49,7 @@
: LiveProcess(params, objFile)
{
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
- brk_point = roundUp(brk_point, VMPageSize);
+ brk_point = roundUp(brk_point, PageBytes);
// Set up stack. On Alpha, stack goes below text section. This
// code should get moved to some architecture-specific spot.
@@ -83,7 +83,7 @@
// seem to be a problem.
// check out _dl_aux_init() in glibc/elf/dl-support.c for details
// --Lisa
- auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::VMPageSize));
+ auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::PageBytes));
auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
DPRINTF(Loader, "auxv at PHDR %08p\n",
elfObject->programHeaderTable());
@@ -193,7 +193,7 @@
LiveProcess::initState();
- argsInit(MachineBytes, VMPageSize);
+ argsInit(MachineBytes, PageBytes);
ThreadContext *tc = system->getThreadContext(contextIds[0]);
tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
diff -r 19f5df7ac6a1 -r 98771a936b61 src/arch/arm/isa_traits.hh
--- a/src/arch/arm/isa_traits.hh Wed Sep 03 07:42:20 2014 -0400
+++ b/src/arch/arm/isa_traits.hh Wed Sep 03 07:42:21 2014 -0400
@@ -51,8 +51,6 @@
namespace LittleEndianGuest {}
-#define TARGET_ARM
-
namespace ArmISA
{
using namespace LittleEndianGuest;
@@ -101,16 +99,7 @@
// return a no-op instruction... used for instruction fetch faults
const ExtMachInst NoopMachInst = 0x01E320F000ULL;
- const int LogVMPageSize = 12; // 4K bytes
- const int VMPageSize = (1 << LogVMPageSize);
-
- // Shouldn't this be 1 because of Thumb?! Dynamic? --Ali
- const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
-
const int MachineBytes = 4;
- const int WordBytes = 4;
- const int HalfwordBytes = 2;
- const int ByteBytes = 1;
const uint32_t HighVecs = 0xFFFF0000;
diff -r 19f5df7ac6a1 -r 98771a936b61 src/arch/arm/process.cc
--- a/src/arch/arm/process.cc Wed Sep 03 07:42:20 2014 -0400
+++ b/src/arch/arm/process.cc Wed Sep 03 07:42:21 2014 -0400
@@ -74,7 +74,7 @@
// Set up break point (Top of Heap)
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
- brk_point = roundUp(brk_point, VMPageSize);
+ brk_point = roundUp(brk_point, PageBytes);
// Set up region for mmaps. For now, start at bottom of kuseg space.
mmap_start = mmap_end = 0x40000000L;
@@ -91,7 +91,7 @@
// Set up break point (Top of Heap)
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
- brk_point = roundUp(brk_point, VMPageSize);
+ brk_point = roundUp(brk_point, PageBytes);
// Set up region for mmaps. For now, start at bottom of kuseg space.
mmap_start = mmap_end = 0x4000000000L;
@@ -101,7 +101,7 @@
ArmLiveProcess32::initState()
{
LiveProcess::initState();
- argsInit<uint32_t>(VMPageSize, INTREG_SP);
+ argsInit<uint32_t>(PageBytes, INTREG_SP);
for (int i = 0; i < contextIds.size(); i++) {
ThreadContext * tc = system->getThreadContext(contextIds[i]);
CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
@@ -120,7 +120,7 @@
ArmLiveProcess64::initState()
{
LiveProcess::initState();
- argsInit<uint64_t>(VMPageSize, INTREG_SP0);
+ argsInit<uint64_t>(PageBytes, INTREG_SP0);
for (int i = 0; i < contextIds.size(); i++) {
ThreadContext * tc = system->getThreadContext(contextIds[i]);
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
@@ -203,7 +203,7 @@
//XXX Figure out what these should be
auxv.push_back(auxv_t(M5_AT_HWCAP, features));
//The system page size
- auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::VMPageSize));
+ auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::PageBytes));
//Frequency at which times() increments
auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64));
// For statically linked executables, this is the virtual address of
the
diff -r 19f5df7ac6a1 -r 98771a936b61 src/arch/arm/utility.cc
--- a/src/arch/arm/utility.cc Wed Sep 03 07:42:20 2014 -0400
+++ b/src/arch/arm/utility.cc Wed Sep 03 07:42:21 2014 -0400
@@ -85,6 +85,7 @@
}
} else {
if (size == (uint16_t)(-1))
+ // todo: should this not be sizeof(uint32_t) rather?
size = ArmISA::MachineBytes;
if (number < NumArgumentRegs) {
diff -r 19f5df7ac6a1 -r 98771a936b61 src/arch/mips/isa_traits.hh
--- a/src/arch/mips/isa_traits.hh Wed Sep 03 07:42:20 2014 -0400
+++ b/src/arch/mips/isa_traits.hh Wed Sep 03 07:42:21 2014 -0400
@@ -145,16 +145,6 @@
// return a no-op instruction... used for instruction fetch faults
const ExtMachInst NoopMachInst = 0x00000000;
-const int LogVMPageSize = 13; // 8K bytes
-const int VMPageSize = (1 << LogVMPageSize);
-
-const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
-
-const int MachineBytes = 4;
-const int WordBytes = 4;
-const int HalfwordBytes = 2;
-const int ByteBytes = 1;
-
const int ANNOTE_NONE = 0;
const uint32_t ITOUCH_ANNOTE = 0xffffffff;
diff -r 19f5df7ac6a1 -r 98771a936b61 src/arch/mips/process.cc
--- a/src/arch/mips/process.cc Wed Sep 03 07:42:20 2014 -0400
+++ b/src/arch/mips/process.cc Wed Sep 03 07:42:21 2014 -0400
@@ -58,7 +58,7 @@
// Set up break point (Top of Heap)
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
- brk_point = roundUp(brk_point, VMPageSize);
+ brk_point = roundUp(brk_point, PageBytes);
// Set up region for mmaps. Start it 1GB above the top of the heap.
mmap_start = mmap_end = brk_point + 0x40000000L;
@@ -69,7 +69,7 @@
{
LiveProcess::initState();
- argsInit<uint32_t>(VMPageSize);
+ argsInit<uint32_t>(PageBytes);
}
template<class IntType>
@@ -88,7 +88,7 @@
if (elfObject)
{
// Set the system page size
- auxv.push_back(auxv_t(M5_AT_PAGESZ, MipsISA::VMPageSize));
+ auxv.push_back(auxv_t(M5_AT_PAGESZ, MipsISA::PageBytes));
// Set the frequency at which time() increments
auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
// For statically linked executables, this is the virtual
diff -r 19f5df7ac6a1 -r 98771a936b61 src/arch/null/isa_traits.hh
--- a/src/arch/null/isa_traits.hh Wed Sep 03 07:42:20 2014 -0400
+++ b/src/arch/null/isa_traits.hh Wed Sep 03 07:42:21 2014 -0400
@@ -51,9 +51,6 @@
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
- const int LogVMPageSize = 12; // 4K bytes
- const int VMPageSize = (1 << LogVMPageSize);
-
}
#endif //__ARCH_NULL_ISA_TRAITS_HH__
diff -r 19f5df7ac6a1 -r 98771a936b61 src/arch/power/isa_traits.hh
--- a/src/arch/power/isa_traits.hh Wed Sep 03 07:42:20 2014 -0400
+++ b/src/arch/power/isa_traits.hh Wed Sep 03 07:42:21 2014 -0400
@@ -61,9 +61,6 @@
const Addr NPtePage = ULL(1) << NPtePageShift;
const Addr PteMask = NPtePage - 1;
-const int LogVMPageSize = 12; // 4K bytes
-const int VMPageSize = (1 << LogVMPageSize);
-
const int MachineBytes = 4;
// This is ori 0, 0, 0
diff -r 19f5df7ac6a1 -r 98771a936b61 src/arch/power/process.cc
--- a/src/arch/power/process.cc Wed Sep 03 07:42:20 2014 -0400
+++ b/src/arch/power/process.cc Wed Sep 03 07:42:21 2014 -0400
@@ -56,7 +56,7 @@
// Set up break point (Top of Heap)
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
- brk_point = roundUp(brk_point, VMPageSize);
+ brk_point = roundUp(brk_point, PageBytes);
// Set up region for mmaps. For now, start at bottom of kuseg space.
mmap_start = mmap_end = 0x70000000L;
@@ -67,7 +67,7 @@
{
Process::initState();
- argsInit(MachineBytes, VMPageSize);
+ argsInit(MachineBytes, PageBytes);
}
void
@@ -98,7 +98,7 @@
//XXX Figure out what these should be
auxv.push_back(auxv_t(M5_AT_HWCAP, features));
//The system page size
- auxv.push_back(auxv_t(M5_AT_PAGESZ, PowerISA::VMPageSize));
+ auxv.push_back(auxv_t(M5_AT_PAGESZ, PowerISA::PageBytes));
//Frequency at which times() increments
auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64));
// For statically linked executables, this is the virtual address of
the
diff -r 19f5df7ac6a1 -r 98771a936b61 src/arch/sparc/isa_traits.hh
--- a/src/arch/sparc/isa_traits.hh Wed Sep 03 07:42:20 2014 -0400
+++ b/src/arch/sparc/isa_traits.hh Wed Sep 03 07:42:21 2014 -0400
@@ -41,8 +41,6 @@
namespace SparcISA
{
-const int MachineBytes = 8;
-
// This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest;
@@ -52,21 +50,13 @@
// SPARC NOP (sethi %(hi(0), g0)
const MachInst NoopMachInst = 0x01000000;
-// 8K. This value is implmentation specific; and should probably
-// be somewhere else.
-const int LogVMPageSize = 13;
-const int VMPageSize = (1 << LogVMPageSize);
-
// real address virtual mapping
// sort of like alpha super page, but less frequently used
const Addr SegKPMEnd = ULL(0xfffffffc00000000);
const Addr SegKPMBase = ULL(0xfffffac000000000);
-// Why does both the previous set of constants and this one exist?
-const int PageShift = 13;
-const int PageBytes = 1ULL << PageShift;
-
-const int BranchPredAddrShiftAmt = 2;
+const Addr PageShift = 13;
+const Addr PageBytes = ULL(1) << PageShift;
StaticInstPtr decodeInst(ExtMachInst);
diff -r 19f5df7ac6a1 -r 98771a936b61 src/arch/sparc/process.cc
--- a/src/arch/sparc/process.cc Wed Sep 03 07:42:20 2014 -0400
+++ b/src/arch/sparc/process.cc Wed Sep 03 07:42:21 2014 -0400
@@ -57,7 +57,7 @@
// XXX all the below need to be updated for SPARC - Ali
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
- brk_point = roundUp(brk_point, VMPageSize);
+ brk_point = roundUp(brk_point, PageBytes);
// Set pointer for next thread stack. Reserve 8M for main stack.
next_thread_stack_base = stack_base - (8 * 1024 * 1024);
@@ -166,7 +166,7 @@
pstate.am = 1;
tc->setMiscReg(MISCREG_PSTATE, pstate);
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