changeset 35241e33c38f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=35241e33c38f
description:
alpha: Stop using 'inorder' and rely entirely on 'minor'
This patch avoids building the 'inorder' CPU model for any permutation
of ALPHA, and also removes the ALPHA regressions using the 'inorder'
CPU. The 'minor' CPU is already providing a broader test coverage.
diffstat:
build_opts/ALPHA | 2 +-
build_opts/ALPHA_MESI_Two_Level | 2 +-
build_opts/ALPHA_MOESI_CMP_directory | 2 +-
build_opts/ALPHA_MOESI_CMP_token | 2 +-
build_opts/ALPHA_MOESI_hammer | 2 +-
build_opts/ALPHA_Network_test | 2 +-
tests/SConscript | 1 -
tests/configs/tsunami-inorder.py | 43 -
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini | 346 ----
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr | 51 -
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout | 14 -
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt | 721
---------
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini | 346 ----
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr | 5 -
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout | 11 -
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg | 158 --
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out | 258 ---
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt | 752
---------
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini | 346 ----
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr | 5 -
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout | 26 -
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt | 759
----------
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini | 346 ----
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr | 5 -
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout | 26 -
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out | 276 ---
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin | 17 -
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1 | 11 -
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2 | 2 -
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav | 18 -
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2 | 19 -
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf | 29 -
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | 722
---------
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini | 346 ----
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr | 1 -
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout | 12 -
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt | 699
---------
37 files changed, 6 insertions(+), 6377 deletions(-)
diffs (truncated from 6560 to 300 lines):
diff -r 939094c17866 -r 35241e33c38f build_opts/ALPHA
--- a/build_opts/ALPHA Wed Sep 03 07:42:55 2014 -0400
+++ b/build_opts/ALPHA Wed Sep 03 07:42:56 2014 -0400
@@ -1,4 +1,4 @@
TARGET_ISA = 'alpha'
SS_COMPATIBLE_FP = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU,MinorCPU'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MI_example'
diff -r 939094c17866 -r 35241e33c38f build_opts/ALPHA_MESI_Two_Level
--- a/build_opts/ALPHA_MESI_Two_Level Wed Sep 03 07:42:55 2014 -0400
+++ b/build_opts/ALPHA_MESI_Two_Level Wed Sep 03 07:42:56 2014 -0400
@@ -1,3 +1,3 @@
SS_COMPATIBLE_FP = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MESI_Two_Level'
diff -r 939094c17866 -r 35241e33c38f build_opts/ALPHA_MOESI_CMP_directory
--- a/build_opts/ALPHA_MOESI_CMP_directory Wed Sep 03 07:42:55 2014 -0400
+++ b/build_opts/ALPHA_MOESI_CMP_directory Wed Sep 03 07:42:56 2014 -0400
@@ -1,3 +1,3 @@
SS_COMPATIBLE_FP = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MOESI_CMP_directory'
diff -r 939094c17866 -r 35241e33c38f build_opts/ALPHA_MOESI_CMP_token
--- a/build_opts/ALPHA_MOESI_CMP_token Wed Sep 03 07:42:55 2014 -0400
+++ b/build_opts/ALPHA_MOESI_CMP_token Wed Sep 03 07:42:56 2014 -0400
@@ -1,3 +1,3 @@
SS_COMPATIBLE_FP = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MOESI_CMP_token'
diff -r 939094c17866 -r 35241e33c38f build_opts/ALPHA_MOESI_hammer
--- a/build_opts/ALPHA_MOESI_hammer Wed Sep 03 07:42:55 2014 -0400
+++ b/build_opts/ALPHA_MOESI_hammer Wed Sep 03 07:42:56 2014 -0400
@@ -1,3 +1,3 @@
SS_COMPATIBLE_FP = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MOESI_hammer'
diff -r 939094c17866 -r 35241e33c38f build_opts/ALPHA_Network_test
--- a/build_opts/ALPHA_Network_test Wed Sep 03 07:42:55 2014 -0400
+++ b/build_opts/ALPHA_Network_test Wed Sep 03 07:42:56 2014 -0400
@@ -1,3 +1,3 @@
SS_COMPATIBLE_FP = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'Network_test'
diff -r 939094c17866 -r 35241e33c38f tests/SConscript
--- a/tests/SConscript Wed Sep 03 07:42:55 2014 -0400
+++ b/tests/SConscript Wed Sep 03 07:42:56 2014 -0400
@@ -307,7 +307,6 @@
'twosys-tsunami-simple-atomic',
'tsunami-o3', 'tsunami-o3-dual',
'tsunami-minor', 'tsunami-minor-dual',
- 'tsunami-inorder',
'tsunami-switcheroo-full']
if env['TARGET_ISA'] == 'sparc':
configs += ['t1000-simple-atomic',
diff -r 939094c17866 -r 35241e33c38f tests/configs/tsunami-inorder.py
--- a/tests/configs/tsunami-inorder.py Wed Sep 03 07:42:55 2014 -0400
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,43 +0,0 @@
-# Copyright (c) 2012 ARM Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder. You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Andreas Sandberg
-
-from m5.objects import *
-from alpha_generic import *
-
-root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
- mem_class=DDR3_1600_x64,
- cpu_class=InOrderCPU).create_root()
diff -r 939094c17866 -r 35241e33c38f
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini Wed Sep
03 07:42:55 2014 -0400
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,346 +0,0 @@
-[root]
-type=Root
-children=system
-eventq_index=0
-full_system=false
-sim_quantum=0
-time_sync_enable=false
-time_sync_period=100000000000
-time_sync_spin_threshold=100000000
-
-[system]
-type=System
-children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem
voltage_domain
-boot_osflags=a
-cache_line_size=64
-clk_domain=system.clk_domain
-eventq_index=0
-init_param=0
-kernel=
-kernel_addr_check=true
-load_addr_mask=1099511627775
-load_offset=0
-mem_mode=timing
-mem_ranges=
-memories=system.physmem
-num_work_ids=16
-readfile=
-symbolfile=
-work_begin_ckpt_count=0
-work_begin_cpu_id_exit=-1
-work_begin_exit_count=0
-work_cpus_ckpt_count=0
-work_end_ckpt_count=0
-work_end_exit_count=0
-work_item_id=-1
-system_port=system.membus.slave[0]
-
-[system.clk_domain]
-type=SrcClockDomain
-clock=1000
-domain_id=-1
-eventq_index=0
-init_perf_level=0
-voltage_domain=system.voltage_domain
-
-[system.cpu]
-type=InOrderCPU
-children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus
tracer workload
-activity=0
-branchPred=system.cpu.branchPred
-cachePorts=2
-checker=Null
-clk_domain=system.cpu_clk_domain
-cpu_id=0
-div16Latency=1
-div16RepeatRate=1
-div24Latency=1
-div24RepeatRate=1
-div32Latency=1
-div32RepeatRate=1
-div8Latency=1
-div8RepeatRate=1
-do_checkpoint_insts=true
-do_quiesce=true
-do_statistics_insts=true
-dtb=system.cpu.dtb
-eventq_index=0
-fetchBuffSize=4
-function_trace=false
-function_trace_start=0
-interrupts=system.cpu.interrupts
-isa=system.cpu.isa
-itb=system.cpu.itb
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-memBlockSize=64
-multLatency=1
-multRepeatRate=1
-numThreads=1
-profile=0
-progress_interval=0
-simpoint_start_insts=
-socket_id=0
-stageTracing=false
-stageWidth=4
-switched_out=false
-system=system
-threadModel=SMT
-tracer=system.cpu.tracer
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.branchPred]
-type=BranchPredictor
-BTBEntries=4096
-BTBTagSize=16
-RASSize=16
-choiceCtrBits=2
-choicePredictorSize=8192
-eventq_index=0
-globalCtrBits=2
-globalPredictorSize=8192
-instShiftAmt=2
-localCtrBits=2
-localHistoryTableSize=2048
-localPredictorSize=2048
-numThreads=1
-predType=tournament
-
-[system.cpu.dcache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=262144
-system=system
-tags=system.cpu.dcache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.slave[1]
-
-[system.cpu.dcache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=262144
-
-[system.cpu.dtb]
-type=AlphaTLB
-eventq_index=0
-size=64
-
-[system.cpu.icache]
-type=BaseCache
-children=tags
-addr_ranges=0:18446744073709551615
-assoc=2
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-forward_snoops=true
-hit_latency=2
-is_top_level=true
-max_miss_count=0
-mshrs=4
-prefetch_on_access=false
-prefetcher=Null
-response_latency=2
-sequential_access=false
-size=131072
-system=system
-tags=system.cpu.icache.tags
-tgts_per_mshr=20
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.slave[0]
-
-[system.cpu.icache.tags]
-type=LRU
-assoc=2
-block_size=64
-clk_domain=system.cpu_clk_domain
-eventq_index=0
-hit_latency=2
-sequential_access=false
-size=131072
-
-[system.cpu.interrupts]
-type=AlphaInterrupts
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