changeset 1ba825974ee6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1ba825974ee6
description:
cpu: Fix o3 quiesce fetch bug
O3 is supposed to stop fetching instructions once a quiesce is
encountered.
However due to a bug, it would continue fetching instructions from the
current
fetch buffer. This is because of a break statment that only broke out
of the
first of 2 nested loops. It should have broken out of both.
diffstat:
src/cpu/o3/fetch_impl.hh | 8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)
diffs (34 lines):
diff -r ed05298e8566 -r 1ba825974ee6 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Wed Sep 03 07:42:37 2014 -0400
+++ b/src/cpu/o3/fetch_impl.hh Wed Sep 03 07:42:38 2014 -0400
@@ -1236,6 +1236,9 @@
// ended this fetch block.
bool predictedBranch = false;
+ // Need to halt fetch if quiesce instruction detected
+ bool quiesce = false;
+
TheISA::MachInst *cacheInsts =
reinterpret_cast<TheISA::MachInst *>(fetchBuffer[tid]);
@@ -1246,7 +1249,7 @@
// Keep issuing while fetchWidth is available and branch is not
// predicted taken
while (numInst < fetchWidth && fetchQueue[tid].size() < fetchQueueSize
- && !predictedBranch) {
+ && !predictedBranch && !quiesce) {
// We need to process more memory if we aren't going to get a
// StaticInst from the rom, the current macroop, or what's already
// in the decoder.
@@ -1363,9 +1366,10 @@
if (instruction->isQuiesce()) {
DPRINTF(Fetch,
- "Quiesce instruction encountered, halting fetch!");
+ "Quiesce instruction encountered, halting fetch!\n");
fetchStatus[tid] = QuiescePending;
status_change = true;
+ quiesce = true;
break;
}
} while ((curMacroop || decoder[tid]->instReady()) &&
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