changeset 1e2f39859382 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1e2f39859382
description:
dev: seperate legacy io offsets from PCI offset
The PC platform has a single IO range that is used both legacy IO and
PCI IO
while other platforms may use seperate regions. Provide another
mechanism to
configure the legacy IO base address range and set it to the PCI IO
address
range for x86.
diffstat:
src/dev/Pci.py | 1 +
src/dev/pcidev.cc | 2 +-
src/dev/x86/SouthBridge.py | 1 +
3 files changed, 3 insertions(+), 1 deletions(-)
diffs (34 lines):
diff -r 644b615fbe6a -r 1e2f39859382 src/dev/Pci.py
--- a/src/dev/Pci.py Wed Sep 03 07:43:05 2014 -0400
+++ b/src/dev/Pci.py Wed Sep 03 07:43:06 2014 -0400
@@ -98,6 +98,7 @@
BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO")
BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO")
BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO")
+ LegacyIOBase = Param.Addr(0x0, "Base Address for Legacy IO")
CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
SubsystemID = Param.UInt16(0x00, "Subsystem ID")
diff -r 644b615fbe6a -r 1e2f39859382 src/dev/pcidev.cc
--- a/src/dev/pcidev.cc Wed Sep 03 07:43:05 2014 -0400
+++ b/src/dev/pcidev.cc Wed Sep 03 07:43:06 2014 -0400
@@ -213,7 +213,7 @@
for (int i = 0; i < 6; ++i) {
if (legacyIO[i]) {
- BARAddrs[i] = platform->calcPciIOAddr(letoh(config.baseAddr[i]));
+ BARAddrs[i] = p->LegacyIOBase + letoh(config.baseAddr[i]);
config.baseAddr[i] = 0;
} else {
BARAddrs[i] = 0;
diff -r 644b615fbe6a -r 1e2f39859382 src/dev/x86/SouthBridge.py
--- a/src/dev/x86/SouthBridge.py Wed Sep 03 07:43:05 2014 -0400
+++ b/src/dev/x86/SouthBridge.py Wed Sep 03 07:43:06 2014 -0400
@@ -84,6 +84,7 @@
ide.ProgIF = 0x80
ide.InterruptLine = 14
ide.InterruptPin = 1
+ ide.LegacyIOBase = x86IOAddress(0)
def attachIO(self, bus, dma_ports):
# Route interupt signals
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