----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/2398/ -----------------------------------------------------------
Review request for Default. Repository: gem5 Description ------- Changeset 10391:6f4a19eeaea0 --------------------------- mem: Rename Bus to XBar to better reflect its behaviour This patch changes the name of the Bus classes to XBar to better reflect the actual timing behaviour. The actual instances in the config scripts are not renamed, and remain as e.g. iobus or membus. As part of this renaming, the code has also been clean up slightly, making use of range-based for loops and tidying up some comments. The only changes outside the bus/crossbar code is due to the delay variables in the packet. Diffs ----- configs/common/CacheConfig.py e2c43045a81b configs/common/FSConfig.py e2c43045a81b configs/dram/sweep.py e2c43045a81b configs/example/memtest.py e2c43045a81b configs/example/ruby_mem_test.py e2c43045a81b configs/example/se.py e2c43045a81b configs/splash2/cluster.py e2c43045a81b configs/splash2/run.py e2c43045a81b src/arch/x86/pagetable_walker.cc e2c43045a81b src/cpu/BaseCPU.py e2c43045a81b src/dev/io_device.cc e2c43045a81b src/dev/pcidev.cc e2c43045a81b src/dev/x86/intdev.hh e2c43045a81b src/mem/Bus.py e2c43045a81b src/mem/SConscript e2c43045a81b src/mem/XBar.py PRE-CREATION src/mem/bridge.hh e2c43045a81b src/mem/bridge.cc e2c43045a81b src/mem/bus.hh e2c43045a81b src/mem/bus.cc e2c43045a81b src/mem/cache/cache_impl.hh e2c43045a81b src/mem/coherent_bus.hh e2c43045a81b src/mem/coherent_bus.cc e2c43045a81b src/mem/coherent_xbar.hh PRE-CREATION src/mem/coherent_xbar.cc PRE-CREATION src/mem/dram_ctrl.cc e2c43045a81b src/mem/dramsim2.cc e2c43045a81b src/mem/noncoherent_bus.hh e2c43045a81b src/mem/noncoherent_bus.cc e2c43045a81b src/mem/noncoherent_xbar.hh PRE-CREATION src/mem/noncoherent_xbar.cc PRE-CREATION src/mem/packet.hh e2c43045a81b src/mem/physical.cc e2c43045a81b src/mem/simple_mem.cc e2c43045a81b src/mem/xbar.hh PRE-CREATION src/mem/xbar.cc PRE-CREATION src/python/m5/params.py e2c43045a81b src/python/m5/util/dot_writer.py e2c43045a81b tests/configs/base_config.py e2c43045a81b tests/configs/memtest-filter.py PRE-CREATION tests/configs/memtest-ruby.py e2c43045a81b tests/configs/memtest.py e2c43045a81b tests/configs/o3-timing-mp-ruby.py e2c43045a81b tests/configs/o3-timing-ruby.py e2c43045a81b tests/configs/simple-atomic-mp-ruby.py e2c43045a81b tests/configs/tgen-dram-ctrl.py e2c43045a81b tests/configs/tgen-simple-mem.py e2c43045a81b Diff: http://reviews.gem5.org/r/2398/diff/ Testing ------- Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
