changeset bf52480abd01 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bf52480abd01
description:
style: Fix line continuation, especially in debug messages
This patch closes a number of space gaps in debug messages caused by
the incorrect use of line continuation within strings. (There's also
one consistency change to a similar, but correct, use of line
continuation)
diffstat:
src/arch/arm/faults.cc | 4 ++--
src/arch/arm/table_walker.cc | 4 ++--
src/arch/arm/tlb.cc | 10 +++++-----
src/cpu/checker/cpu.cc | 4 ++--
src/dev/arm/pl111.cc | 8 ++++----
src/dev/ns_gige.cc | 4 ++--
src/sim/stat_control.cc | 4 ++--
src/sim/system.cc | 7 ++++---
8 files changed, 23 insertions(+), 22 deletions(-)
diffs (146 lines):
diff -r 128c1ed03f4e -r bf52480abd01 src/arch/arm/faults.cc
--- a/src/arch/arm/faults.cc Fri Sep 12 10:22:46 2014 -0400
+++ b/src/arch/arm/faults.cc Fri Sep 12 10:22:47 2014 -0400
@@ -1120,8 +1120,8 @@
if (to64) {
// AArch64
if (source == ArmFault::AsynchronousExternalAbort) {
- panic("Asynchronous External Abort should be handled with \
- SystemErrors (SErrors)!");
+ panic("Asynchronous External Abort should be handled with "
+ "SystemErrors (SErrors)!");
}
if (toEL == fromEL)
return EC_DATA_ABORT_CURR_EL;
diff -r 128c1ed03f4e -r bf52480abd01 src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc Fri Sep 12 10:22:46 2014 -0400
+++ b/src/arch/arm/table_walker.cc Fri Sep 12 10:22:47 2014 -0400
@@ -1116,8 +1116,8 @@
}
}
}
- DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \
- outerAttrs: %d\n",
+ DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, "
+ "outerAttrs: %d\n",
te.shareable, te.innerAttrs, te.outerAttrs);
te.setAttributes(false);
}
diff -r 128c1ed03f4e -r bf52480abd01 src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Fri Sep 12 10:22:46 2014 -0400
+++ b/src/arch/arm/tlb.cc Fri Sep 12 10:22:47 2014 -0400
@@ -163,7 +163,7 @@
retval ? retval->pAddr(va) : 0, retval ? retval->ap : 0,
retval ? retval->ns : 0, retval ? retval->nstid : 0,
retval ? retval->global : 0, retval ? retval->asid : 0,
- retval ? retval->el : 0, retval ? retval->el : 0);
+ retval ? retval->el : 0);
return retval;
}
@@ -1027,8 +1027,8 @@
temp_te.outerShareable = false;
}
temp_te.setAttributes(long_desc_format);
- DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\
- %d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n",
+ DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable: "
+ "%d, innerAttrs: %d, outerAttrs: %d, isStage2: %d\n",
temp_te.shareable, temp_te.innerAttrs, temp_te.outerAttrs,
isStage2);
setAttr(temp_te.attributes);
@@ -1052,8 +1052,8 @@
if (te != NULL) {
// Set memory attributes
DPRINTF(TLBVerbose,
- "Setting memory attributes: shareable: %d, innerAttrs: %d, \
- outerAttrs: %d, mtype: %d, isStage2: %d\n",
+ "Setting memory attributes: shareable: %d, innerAttrs: %d, "
+ "outerAttrs: %d, mtype: %d, isStage2: %d\n",
te->shareable, te->innerAttrs, te->outerAttrs,
static_cast<uint8_t>(te->mtype), isStage2);
setAttr(te->attributes);
diff -r 128c1ed03f4e -r bf52480abd01 src/cpu/checker/cpu.cc
--- a/src/cpu/checker/cpu.cc Fri Sep 12 10:22:46 2014 -0400
+++ b/src/cpu/checker/cpu.cc Fri Sep 12 10:22:47 2014 -0400
@@ -306,8 +306,8 @@
if (unverifiedReq && unverifiedMemData &&
memcmp(data, unverifiedMemData, fullSize) && extraData) {
- warn("%lli: Store value does not match value sent to memory!\
- data: %#x inst_data: %#x", curTick(), data,
+ warn("%lli: Store value does not match value sent to memory! "
+ "data: %#x inst_data: %#x", curTick(), data,
unverifiedMemData);
handleError();
}
diff -r 128c1ed03f4e -r bf52480abd01 src/dev/arm/pl111.cc
--- a/src/dev/arm/pl111.cc Fri Sep 12 10:22:46 2014 -0400
+++ b/src/dev/arm/pl111.cc Fri Sep 12 10:22:47 2014 -0400
@@ -196,8 +196,8 @@
data = lcdPalette[index];
break;
} else {
- panic("Tried to read CLCD register at offset %#x that \
- doesn't exist\n", daddr);
+ panic("Tried to read CLCD register at offset %#x that "
+ "doesn't exist\n", daddr);
break;
}
}
@@ -369,8 +369,8 @@
lcdPalette[index] = data;
break;
} else {
- panic("Tried to write PL111 register at offset %#x that \
- doesn't exist\n", daddr);
+ panic("Tried to write PL111 register at offset %#x that "
+ "doesn't exist\n", daddr);
break;
}
}
diff -r 128c1ed03f4e -r bf52480abd01 src/dev/ns_gige.cc
--- a/src/dev/ns_gige.cc Fri Sep 12 10:22:46 2014 -0400
+++ b/src/dev/ns_gige.cc Fri Sep 12 10:22:47 2014 -0400
@@ -732,8 +732,8 @@
= (uint8_t)(reg >> 8);
break;
}
- panic("writing RFDR for something other than pattern matching\
- or hashing! %#x\n", rfaddr);
+ panic("writing RFDR for something other than pattern matching "
+ "or hashing! %#x\n", rfaddr);
}
case BRAR:
diff -r 128c1ed03f4e -r bf52480abd01 src/sim/stat_control.cc
--- a/src/sim/stat_control.cc Fri Sep 12 10:22:46 2014 -0400
+++ b/src/sim/stat_control.cc Fri Sep 12 10:22:47 2014 -0400
@@ -157,8 +157,8 @@
finalTick
.functor(statFinalTick)
.name("final_tick")
- .desc("Number of ticks from beginning of simulation \
-(restored from checkpoints and never reset)")
+ .desc("Number of ticks from beginning of simulation "
+ "(restored from checkpoints and never reset)")
;
hostInstRate
diff -r 128c1ed03f4e -r bf52480abd01 src/sim/system.cc
--- a/src/sim/system.cc Fri Sep 12 10:22:46 2014 -0400
+++ b/src/sim/system.cc Fri Sep 12 10:22:47 2014 -0400
@@ -450,9 +450,10 @@
// Otherwise objects will have sized their stat buckets and
// they will be too small
- if (Stats::enabled())
- fatal("Can't request a masterId after regStats(). \
- You must do so in init().\n");
+ if (Stats::enabled()) {
+ fatal("Can't request a masterId after regStats(). "
+ "You must do so in init().\n");
+ }
masterIds.push_back(master_name);
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