changeset ab8b8601b6ff in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ab8b8601b6ff
description:
cpu: use probes infrastructure to do simpoint profiling
Instead of having code embedded in cpu model to do simpoint profiling
use
the probes infrastructure to do it.
diffstat:
configs/example/se.py | 3 +-
src/cpu/simple/AtomicSimpleCPU.py | 9 +-
src/cpu/simple/atomic.cc | 97 +++----------------------
src/cpu/simple/atomic.hh | 70 +-----------------
src/cpu/simple/probes/SConscript | 35 +++++++++
src/cpu/simple/probes/SimPoint.py | 48 ++++++++++++
src/cpu/simple/probes/simpoint.cc | 145 ++++++++++++++++++++++++++++++++++++++
src/cpu/simple/probes/simpoint.hh | 119 +++++++++++++++++++++++++++++++
8 files changed, 372 insertions(+), 154 deletions(-)
diffs (truncated from 640 to 300 lines):
diff -r ec1af95a2958 -r ab8b8601b6ff configs/example/se.py
--- a/configs/example/se.py Sat Sep 20 17:17:42 2014 -0400
+++ b/configs/example/se.py Sat Sep 20 17:17:43 2014 -0400
@@ -213,8 +213,7 @@
system.cpu[i].fastmem = True
if options.simpoint_profile:
- system.cpu[i].simpoint_profile = True
- system.cpu[i].simpoint_interval = options.simpoint_interval
+ system.cpu[i].addSimPointProbe(options.simpoint_interval)
if options.checker:
system.cpu[i].addCheckerCpu()
diff -r ec1af95a2958 -r ab8b8601b6ff src/cpu/simple/AtomicSimpleCPU.py
--- a/src/cpu/simple/AtomicSimpleCPU.py Sat Sep 20 17:17:42 2014 -0400
+++ b/src/cpu/simple/AtomicSimpleCPU.py Sat Sep 20 17:17:43 2014 -0400
@@ -40,6 +40,7 @@
from m5.params import *
from BaseSimpleCPU import BaseSimpleCPU
+from SimPoint import SimPoint
class AtomicSimpleCPU(BaseSimpleCPU):
"""Simple CPU model executing a configurable number of
@@ -61,6 +62,8 @@
simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
fastmem = Param.Bool(False, "Access memory directly")
- simpoint_profile = Param.Bool(False, "Generate SimPoint BBVs")
- simpoint_interval = Param.UInt64(100000000, "SimPoint Interval Size
(insts)")
- simpoint_profile_file = Param.String("simpoint.bb.gz", "SimPoint BBV file")
+
+ def addSimPointProbe(self, interval):
+ simpoint = SimPoint()
+ simpoint.interval = interval
+ self.probeListener = simpoint
diff -r ec1af95a2958 -r ab8b8601b6ff src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Sat Sep 20 17:17:42 2014 -0400
+++ b/src/cpu/simple/atomic.cc Sat Sep 20 17:17:43 2014 -0400
@@ -110,20 +110,9 @@
drain_manager(NULL),
icachePort(name() + ".icache_port", this),
dcachePort(name() + ".dcache_port", this),
- fastmem(p->fastmem),
- simpoint(p->simpoint_profile),
- intervalSize(p->simpoint_interval),
- intervalCount(0),
- intervalDrift(0),
- simpointStream(NULL),
- currentBBV(0, 0),
- currentBBVInstCount(0)
+ fastmem(p->fastmem)
{
_status = Idle;
-
- if (simpoint) {
- simpointStream = simout.create(p->simpoint_profile_file, false);
- }
}
@@ -132,9 +121,6 @@
if (tickEvent.scheduled()) {
deschedule(tickEvent);
}
- if (simpointStream) {
- simout.close(simpointStream);
- }
}
unsigned int
@@ -574,8 +560,13 @@
fault = curStaticInst->execute(this, traceData);
// keep an instruction count
- if (fault == NoFault)
+ if (fault == NoFault) {
countInst();
+ if (!curStaticInst->isMicroop() ||
+ curStaticInst->isLastMicroop()) {
+ ppCommit->notify(std::make_pair(thread,
curStaticInst));
+ }
+ }
else if (traceData && !DTRACE(ExecFaulting)) {
delete traceData;
traceData = NULL;
@@ -589,13 +580,6 @@
curStaticInst->isFirstMicroop()))
instCnt++;
- // profile for SimPoints if enabled and macro inst is finished
- if (simpoint && curStaticInst && (fault == NoFault) &&
- (!curStaticInst->isMicroop() ||
- curStaticInst->isLastMicroop())) {
- profileSimPoint();
- }
-
Tick stall_ticks = 0;
if (simulate_inst_stalls && icache_access)
stall_ticks += icache_latency;
@@ -627,6 +611,12 @@
schedule(tickEvent, curTick() + latency);
}
+void
+AtomicSimpleCPU::regProbePoints()
+{
+ ppCommit = new ProbePointArg<pair<SimpleThread*, const StaticInstPtr>>
+ (getProbeManager(), "Commit");
+}
void
AtomicSimpleCPU::printAddr(Addr a)
@@ -634,67 +624,6 @@
dcachePort.printAddr(a);
}
-void
-AtomicSimpleCPU::profileSimPoint()
-{
- if (!currentBBVInstCount)
- currentBBV.first = thread->pcState().instAddr();
-
- ++intervalCount;
- ++currentBBVInstCount;
-
- // If inst is control inst, assume end of basic block.
- if (curStaticInst->isControl()) {
- currentBBV.second = thread->pcState().instAddr();
-
- auto map_itr = bbMap.find(currentBBV);
- if (map_itr == bbMap.end()){
- // If a new (previously unseen) basic block is found,
- // add a new unique id, record num of insts and insert into bbMap.
- BBInfo info;
- info.id = bbMap.size() + 1;
- info.insts = currentBBVInstCount;
- info.count = currentBBVInstCount;
- bbMap.insert(std::make_pair(currentBBV, info));
- } else {
- // If basic block is seen before, just increment the count by the
- // number of insts in basic block.
- BBInfo& info = map_itr->second;
- info.count += currentBBVInstCount;
- }
- currentBBVInstCount = 0;
-
- // Reached end of interval if the sum of the current inst count
- // (intervalCount) and the excessive inst count from the previous
- // interval (intervalDrift) is greater than/equal to the interval size.
- if (intervalCount + intervalDrift >= intervalSize) {
- // summarize interval and display BBV info
- std::vector<pair<uint64_t, uint64_t> > counts;
- for (auto map_itr = bbMap.begin(); map_itr != bbMap.end();
- ++map_itr) {
- BBInfo& info = map_itr->second;
- if (info.count != 0) {
- counts.push_back(std::make_pair(info.id, info.count));
- info.count = 0;
- }
- }
- std::sort(counts.begin(), counts.end());
-
- // Print output BBV info
- *simpointStream << "T";
- for (auto cnt_itr = counts.begin(); cnt_itr != counts.end();
- ++cnt_itr) {
- *simpointStream << ":" << cnt_itr->first
- << ":" << cnt_itr->second << " ";
- }
- *simpointStream << "\n";
-
- intervalDrift = (intervalCount + intervalDrift) - intervalSize;
- intervalCount = 0;
- }
- }
-}
-
////////////////////////////////////////////////////////////////////////
//
// AtomicSimpleCPU Simulation Object
diff -r ec1af95a2958 -r ab8b8601b6ff src/cpu/simple/atomic.hh
--- a/src/cpu/simple/atomic.hh Sat Sep 20 17:17:42 2014 -0400
+++ b/src/cpu/simple/atomic.hh Sat Sep 20 17:17:43 2014 -0400
@@ -43,30 +43,9 @@
#ifndef __CPU_SIMPLE_ATOMIC_HH__
#define __CPU_SIMPLE_ATOMIC_HH__
-#include "base/hashmap.hh"
#include "cpu/simple/base.hh"
#include "params/AtomicSimpleCPU.hh"
-
-/**
- * Start and end address of basic block for SimPoint profiling.
- * This structure is used to look up the hash table of BBVs.
- * - first: PC of first inst in basic block
- * - second: PC of last inst in basic block
- */
-typedef std::pair<Addr, Addr> BasicBlockRange;
-
-/** Overload hash function for BasicBlockRange type */
-__hash_namespace_begin
-template <>
-struct hash<BasicBlockRange>
-{
- public:
- size_t operator()(const BasicBlockRange &bb) const {
- return hash<Addr>()(bb.first + bb.second);
- }
-};
-__hash_namespace_end
-
+#include "sim/probe/probe.hh"
class AtomicSimpleCPU : public BaseSimpleCPU
{
@@ -200,49 +179,8 @@
bool dcache_access;
Tick dcache_latency;
- /**
- * Profile basic blocks for SimPoints.
- * Called at every macro inst to increment basic block inst counts and
- * to profile block if end of block.
- */
- void profileSimPoint();
-
- /** Data structures for SimPoints BBV generation
- * @{
- */
-
- /** Whether SimPoint BBV profiling is enabled */
- const bool simpoint;
- /** SimPoint profiling interval size in instructions */
- const uint64_t intervalSize;
-
- /** Inst count in current basic block */
- uint64_t intervalCount;
- /** Excess inst count from previous interval*/
- uint64_t intervalDrift;
- /** Pointer to SimPoint BBV output stream */
- std::ostream *simpointStream;
-
- /** Basic Block information */
- struct BBInfo {
- /** Unique ID */
- uint64_t id;
- /** Num of static insts in BB */
- uint64_t insts;
- /** Accumulated dynamic inst count executed by BB */
- uint64_t count;
- };
-
- /** Hash table containing all previously seen basic blocks */
- m5::hash_map<BasicBlockRange, BBInfo> bbMap;
- /** Currently executing basic block */
- BasicBlockRange currentBBV;
- /** inst count in current basic block */
- uint64_t currentBBVInstCount;
-
- /** @}
- * End of data structures for SimPoints BBV generation
- */
+ /** Probe Points. */
+ ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit;
protected:
@@ -270,6 +208,8 @@
Fault writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res);
+ virtual void regProbePoints();
+
/**
* Print state of address in memory system via PrintReq (for
* debugging).
diff -r ec1af95a2958 -r ab8b8601b6ff src/cpu/simple/probes/SConscript
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/cpu/simple/probes/SConscript Sat Sep 20 17:17:43 2014 -0400
@@ -0,0 +1,35 @@
+# -*- mode:python -*-
+
+# Copyright (c) 2014 ARM Limited
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
