changeset 560aead2320f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=560aead2320f
description:
tests: Add a memtest version using the ideal SnoopFilter
This patch adds a basic regression test for the snoop filter.
diffstat:
tests/SConscript | 2 +-
tests/configs/memtest-filter.py | 87 +
tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini | 610 +++
tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr | 74 +
tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout | 10 +
tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt | 1747
++++++++++
6 files changed, 2529 insertions(+), 1 deletions(-)
diffs (truncated from 2560 to 300 lines):
diff -r b3231fc8ae9d -r 560aead2320f tests/SConscript
--- a/tests/SConscript Fri Apr 25 12:36:16 2014 +0100
+++ b/tests/SConscript Sat Sep 20 17:18:30 2014 -0400
@@ -344,7 +344,7 @@
'inorder-timing',
'minor-timing', 'minor-timing-mp',
'o3-timing', 'o3-timing-mp',
- 'rubytest', 'memtest',
+ 'rubytest', 'memtest', 'memtest-filter',
'tgen-simple-mem', 'tgen-dram-ctrl']
if env['PROTOCOL'] != 'None':
diff -r b3231fc8ae9d -r 560aead2320f tests/configs/memtest-filter.py
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/configs/memtest-filter.py Sat Sep 20 17:18:30 2014 -0400
@@ -0,0 +1,87 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+from Caches import *
+
+#MAX CORES IS 8 with the fals sharing method
+nb_cores = 8
+cpus = [ MemTest() for i in xrange(nb_cores) ]
+
+# system simulated
+system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
+ funcbus = NoncoherentBus(),
+ physmem = SimpleMemory(),
+ membus = CoherentBus(width=16, snoop_filter = SnoopFilter()))
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain = system.voltage_domain)
+
+system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16,
+ snoop_filter = SnoopFilter())
+system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+
+# connect l2c to membus
+system.l2c.mem_side = system.membus.slave
+
+# add L1 caches
+for cpu in cpus:
+ # All cpus are associated with cpu_clk_domain
+ cpu.clk_domain = system.cpu_clk_domain
+ cpu.l1c = L1Cache(size = '32kB', assoc = 4)
+ cpu.l1c.cpu_side = cpu.test
+ cpu.l1c.mem_side = system.toL2Bus.slave
+ system.funcbus.slave = cpu.functional
+
+system.system_port = system.membus.slave
+
+# connect reference memory to funcbus
+system.funcmem.port = system.funcbus.master
+
+# connect memory to membus
+system.physmem.port = system.membus.master
+
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root( full_system = False, system = system )
+root.system.mem_mode = 'timing'
+#root.trace.flags="Cache CachePort MemoryAccess"
+#root.trace.cycle=1
+
diff -r b3231fc8ae9d -r 560aead2320f
tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini Sat Sep
20 17:18:30 2014 -0400
@@ -0,0 +1,610 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain
funcbus funcmem l2c membus physmem toL2Bus voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem system.funcmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+eventq_index=0
+voltage_domain=system.voltage_domain
+
+[system.cpu0]
+type=MemTest
+children=l1c
+atomic=false
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[0]
+test=system.cpu0.l1c.cpu_side
+
+[system.cpu0.l1c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.l1c.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.test
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu1]
+type=MemTest
+children=l1c
+atomic=false
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[1]
+test=system.cpu1.l1c.cpu_side
+
+[system.cpu1.l1c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu1.l1c.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.test
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu2]
+type=MemTest
+children=l1c
+atomic=false
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[2]
+test=system.cpu2.l1c.cpu_side
+
+[system.cpu2.l1c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
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