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Ship it! LGTM, but this one is probably for Brad or similar - Andreas Hansson On Sept. 25, 2014, 4:45 a.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2420/ > ----------------------------------------------------------- > > (Updated Sept. 25, 2014, 4:45 a.m.) > > > Review request for Default. > > > Repository: gem5 > > > Description > ------- > > Changeset 10422:19e535c5fbc6 > --------------------------- > ruby: coherence protocols: remove data block from dirctory entry > This patch removes the data block present in the directory entry structure > of each protocol in gem5's mainline. Firstly, this is required for moving > towards common set of memory controllers for classic and ruby memory systems. > Secondly, the data block was being misused in several places. It was being > used for having free access to the physical memory instead of calling on the > memory controller. > > From now on, the directory controller will not have a direct visibility into > the physical memory. The Memory Vector object now resides in the > Memory Controller class. This also means that some significant changes are > being made to the functional accesses in ruby. > > > Diffs > ----- > > src/mem/protocol/MESI_Three_Level-L0cache.sm d96740732a61 > src/mem/protocol/MESI_Three_Level-L1cache.sm d96740732a61 > src/mem/protocol/MESI_Two_Level-L1cache.sm d96740732a61 > src/mem/protocol/MESI_Two_Level-L2cache.sm d96740732a61 > src/mem/protocol/MESI_Two_Level-dir.sm d96740732a61 > src/mem/protocol/MESI_Two_Level-dma.sm d96740732a61 > src/mem/protocol/MI_example-cache.sm d96740732a61 > src/mem/protocol/MI_example-dir.sm d96740732a61 > src/mem/protocol/MI_example-dma.sm d96740732a61 > src/mem/protocol/MOESI_CMP_directory-L1cache.sm d96740732a61 > src/mem/protocol/MOESI_CMP_directory-L2cache.sm d96740732a61 > src/mem/protocol/MOESI_CMP_directory-dir.sm d96740732a61 > src/mem/protocol/MOESI_CMP_directory-dma.sm d96740732a61 > src/mem/protocol/MOESI_CMP_token-L1cache.sm d96740732a61 > src/mem/protocol/MOESI_CMP_token-L2cache.sm d96740732a61 > src/mem/protocol/MOESI_CMP_token-dir.sm d96740732a61 > src/mem/protocol/MOESI_CMP_token-dma.sm d96740732a61 > src/mem/protocol/MOESI_hammer-cache.sm d96740732a61 > src/mem/protocol/MOESI_hammer-dir.sm d96740732a61 > src/mem/protocol/MOESI_hammer-dma.sm d96740732a61 > src/mem/protocol/Network_test-cache.sm d96740732a61 > src/mem/protocol/Network_test-dir.sm d96740732a61 > src/mem/protocol/RubySlicc_Types.sm d96740732a61 > src/mem/ruby/slicc_interface/AbstractCacheEntry.hh d96740732a61 > src/mem/ruby/slicc_interface/AbstractController.hh d96740732a61 > src/mem/ruby/slicc_interface/AbstractEntry.hh d96740732a61 > src/mem/ruby/structures/DirectoryMemory.hh d96740732a61 > src/mem/ruby/structures/DirectoryMemory.cc d96740732a61 > src/mem/ruby/structures/MemoryControl.hh d96740732a61 > src/mem/ruby/structures/RubyMemoryControl.hh d96740732a61 > src/mem/ruby/structures/RubyMemoryControl.cc d96740732a61 > src/mem/ruby/system/System.cc d96740732a61 > > Diff: http://reviews.gem5.org/r/2420/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
