changeset 710ee116eb68 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=710ee116eb68
description:
arch: Use const StaticInstPtr references where possible
This patch optimises the passing of StaticInstPtr by avoiding copying
the reference-counting pointer. This avoids first incrementing and
then decrementing the reference-counting pointer.
diffstat:
src/arch/alpha/faults.cc | 12 +++++-----
src/arch/alpha/faults.hh | 24 ++++++++++----------
src/arch/alpha/stacktrace.cc | 2 +-
src/arch/alpha/stacktrace.hh | 6 ++--
src/arch/alpha/utility.hh | 2 +-
src/arch/arm/faults.cc | 24 ++++++++++----------
src/arch/arm/faults.hh | 46 +++++++++++++++++++-------------------
src/arch/arm/stacktrace.cc | 2 +-
src/arch/arm/stacktrace.hh | 6 ++--
src/arch/arm/utility.hh | 2 +-
src/arch/generic/debugfaults.hh | 4 +-
src/arch/mips/faults.cc | 8 +++---
src/arch/mips/faults.hh | 28 +++++++++++-----------
src/arch/mips/stacktrace.cc | 2 +-
src/arch/mips/stacktrace.hh | 6 ++--
src/arch/mips/utility.hh | 2 +-
src/arch/power/stacktrace.cc | 2 +-
src/arch/power/stacktrace.hh | 6 ++--
src/arch/power/utility.hh | 2 +-
src/arch/sparc/faults.cc | 15 ++++++-----
src/arch/sparc/faults.hh | 28 +++++++++++-----------
src/arch/sparc/stacktrace.hh | 2 +-
src/arch/sparc/utility.hh | 2 +-
src/arch/x86/faults.cc | 14 +++++-----
src/arch/x86/faults.hh | 32 +++++++++++++-------------
src/arch/x86/stacktrace.cc | 2 +-
src/arch/x86/stacktrace.hh | 6 ++--
src/arch/x86/utility.hh | 2 +-
src/cpu/base_dyn_inst.hh | 8 +++---
src/cpu/base_dyn_inst_impl.hh | 8 +++---
src/cpu/checker/cpu_impl.hh | 2 +-
src/cpu/exetrace.cc | 2 +-
src/cpu/exetrace.hh | 2 +-
src/cpu/minor/func_unit.cc | 2 +-
src/cpu/minor/func_unit.hh | 2 +-
src/cpu/o3/cpu.cc | 5 ++-
src/cpu/o3/cpu.hh | 2 +-
src/cpu/o3/dyn_inst.hh | 5 ++-
src/cpu/o3/dyn_inst_impl.hh | 8 +++---
src/cpu/pred/bpred_unit.hh | 4 +-
src/cpu/pred/bpred_unit_impl.hh | 4 +-
src/cpu/profile.hh | 4 +-
src/cpu/simple/probes/simpoint.cc | 2 +-
src/cpu/timing_expr.cc | 2 +-
src/cpu/timing_expr.hh | 4 +-
src/sim/faults.cc | 10 ++++----
src/sim/faults.hh | 20 ++++++++--------
47 files changed, 194 insertions(+), 191 deletions(-)
diffs (truncated from 1487 to 300 lines):
diff -r dd64a2984966 -r 710ee116eb68 src/arch/alpha/faults.cc
--- a/src/arch/alpha/faults.cc Sat Sep 27 09:08:34 2014 -0400
+++ b/src/arch/alpha/faults.cc Sat Sep 27 09:08:36 2014 -0400
@@ -106,7 +106,7 @@
FaultStat IntegerOverflowFault::_count;
void
-AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+AlphaFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
FaultBase::invoke(tc);
if (!FullSystem)
@@ -130,7 +130,7 @@
}
void
-ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+ArithmeticFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
FaultBase::invoke(tc);
if (!FullSystem)
@@ -139,7 +139,7 @@
}
void
-DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
// Set fault address and flags. Even though we're modeling an
@@ -169,7 +169,7 @@
}
void
-ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
if (!tc->misspeculating()) {
@@ -183,7 +183,7 @@
}
void
-ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+ItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
ItbFault::invoke(tc);
@@ -202,7 +202,7 @@
}
void
-NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+NDtbMissFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
DtbFault::invoke(tc, inst);
diff -r dd64a2984966 -r 710ee116eb68 src/arch/alpha/faults.hh
--- a/src/arch/alpha/faults.hh Sat Sep 27 09:08:34 2014 -0400
+++ b/src/arch/alpha/faults.hh Sat Sep 27 09:08:36 2014 -0400
@@ -48,8 +48,8 @@
virtual bool skipFaultingInstruction() {return false;}
virtual bool setRestartAddress() {return true;}
public:
- void invoke(ThreadContext * tc,
- StaticInstPtr inst = StaticInst::nullStaticInstPtr);
+ void invoke(ThreadContext * tc, const StaticInstPtr &inst =
+ StaticInst::nullStaticInstPtr);
virtual FaultVect vect() = 0;
virtual FaultStat & countStat() = 0;
};
@@ -108,8 +108,8 @@
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
- void invoke(ThreadContext * tc,
- StaticInstPtr inst = StaticInst::nullStaticInstPtr);
+ void invoke(ThreadContext * tc, const StaticInstPtr &inst =
+ StaticInst::nullStaticInstPtr);
};
class InterruptFault : public AlphaFault
@@ -142,8 +142,8 @@
FaultName name() const = 0;
FaultVect vect() = 0;
FaultStat & countStat() = 0;
- void invoke(ThreadContext * tc,
- StaticInstPtr inst = StaticInst::nullStaticInstPtr);
+ void invoke(ThreadContext * tc, const StaticInstPtr &inst =
+ StaticInst::nullStaticInstPtr);
};
class NDtbMissFault : public DtbFault
@@ -160,8 +160,8 @@
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
- void invoke(ThreadContext * tc,
- StaticInstPtr inst = StaticInst::nullStaticInstPtr);
+ void invoke(ThreadContext * tc, const StaticInstPtr &inst =
+ StaticInst::nullStaticInstPtr);
};
class PDtbMissFault : public DtbFault
@@ -238,8 +238,8 @@
FaultName name() const = 0;
FaultVect vect() = 0;
FaultStat & countStat() = 0;
- void invoke(ThreadContext * tc,
- StaticInstPtr inst = StaticInst::nullStaticInstPtr);
+ void invoke(ThreadContext * tc, const StaticInstPtr &inst =
+ StaticInst::nullStaticInstPtr);
};
class ItbPageFault : public ItbFault
@@ -254,8 +254,8 @@
FaultName name() const {return _name;}
FaultVect vect() {return _vect;}
FaultStat & countStat() {return _count;}
- void invoke(ThreadContext * tc,
- StaticInstPtr inst = StaticInst::nullStaticInstPtr);
+ void invoke(ThreadContext * tc, const StaticInstPtr &inst =
+ StaticInst::nullStaticInstPtr);
};
class ItbAcvFault : public ItbFault
diff -r dd64a2984966 -r 710ee116eb68 src/arch/alpha/stacktrace.cc
--- a/src/arch/alpha/stacktrace.cc Sat Sep 27 09:08:34 2014 -0400
+++ b/src/arch/alpha/stacktrace.cc Sat Sep 27 09:08:36 2014 -0400
@@ -122,7 +122,7 @@
{
}
-StackTrace::StackTrace(ThreadContext *_tc, StaticInstPtr inst)
+StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst)
: tc(0), stack(64)
{
trace(_tc, inst);
diff -r dd64a2984966 -r 710ee116eb68 src/arch/alpha/stacktrace.hh
--- a/src/arch/alpha/stacktrace.hh Sat Sep 27 09:08:34 2014 -0400
+++ b/src/arch/alpha/stacktrace.hh Sat Sep 27 09:08:36 2014 -0400
@@ -76,7 +76,7 @@
public:
StackTrace();
- StackTrace(ThreadContext *tc, StaticInstPtr inst);
+ StackTrace(ThreadContext *tc, const StaticInstPtr &inst);
~StackTrace();
void
@@ -87,7 +87,7 @@
}
bool valid() const { return tc != NULL; }
- bool trace(ThreadContext *tc, StaticInstPtr inst);
+ bool trace(ThreadContext *tc, const StaticInstPtr &inst);
public:
const std::vector<Addr> &getstack() const { return stack; }
@@ -111,7 +111,7 @@
};
inline bool
-StackTrace::trace(ThreadContext *tc, StaticInstPtr inst)
+StackTrace::trace(ThreadContext *tc, const StaticInstPtr &inst)
{
if (!inst->isCall() && !inst->isReturn())
return false;
diff -r dd64a2984966 -r 710ee116eb68 src/arch/alpha/utility.hh
--- a/src/arch/alpha/utility.hh Sat Sep 27 09:08:34 2014 -0400
+++ b/src/arch/alpha/utility.hh Sat Sep 27 09:08:36 2014 -0400
@@ -105,7 +105,7 @@
void skipFunction(ThreadContext *tc);
inline void
-advancePC(PCState &pc, const StaticInstPtr inst)
+advancePC(PCState &pc, const StaticInstPtr &inst)
{
pc.advance();
}
diff -r dd64a2984966 -r 710ee116eb68 src/arch/arm/faults.cc
--- a/src/arch/arm/faults.cc Sat Sep 27 09:08:34 2014 -0400
+++ b/src/arch/arm/faults.cc Sat Sep 27 09:08:36 2014 -0400
@@ -426,7 +426,7 @@
}
void
-ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
@@ -587,7 +587,7 @@
}
void
-ArmFault::invoke64(ThreadContext *tc, StaticInstPtr inst)
+ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
{
// Determine actual misc. register indices for ELR_ELx and SPSR_ELx
MiscRegIndex elr_idx, spsr_idx;
@@ -678,7 +678,7 @@
}
void
-Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
+Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
tc->getCpuPtr()->clearInterrupts();
@@ -706,7 +706,7 @@
}
void
-UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
+UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
ArmFault::invoke(tc, inst);
@@ -767,7 +767,7 @@
}
void
-SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
+SupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
ArmFault::invoke(tc, inst);
@@ -884,7 +884,7 @@
// }
void
-SecureMonitorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
+SecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (FullSystem) {
ArmFault::invoke(tc, inst);
@@ -913,7 +913,7 @@
template<class T>
void
-AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
+AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
if (tranMethod == ArmFault::UnknownTran) {
tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran
@@ -1237,7 +1237,7 @@
}
void
-VirtualDataAbort::invoke(ThreadContext *tc, StaticInstPtr inst)
+VirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
AbortFault<VirtualDataAbort>::invoke(tc, inst);
HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
@@ -1336,7 +1336,7 @@
{}
void
-PCAlignmentFault::invoke(ThreadContext *tc, StaticInstPtr inst)
+PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
ArmFaultVals<PCAlignmentFault>::invoke(tc, inst);
assert(from64);
@@ -1351,7 +1351,7 @@
{}
void
-SystemError::invoke(ThreadContext *tc, StaticInstPtr inst)
+SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst)
{
tc->getCpuPtr()->clearInterrupt(INT_ABT, 0);
ArmFault::invoke(tc, inst);
@@ -1382,7 +1382,7 @@
}
void
-FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
+FlushPipe::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
DPRINTF(Faults, "Invoking FlushPipe Fault\n");
// Set the PC to the next instruction of the faulting instruction.
@@ -1395,7 +1395,7 @@
}
void
-ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) {
+ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
DPRINTF(Faults, "Invoking ArmSev Fault\n");
if (!FullSystem)
return;
diff -r dd64a2984966 -r 710ee116eb68 src/arch/arm/faults.hh
--- a/src/arch/arm/faults.hh Sat Sep 27 09:08:34 2014 -0400
+++ b/src/arch/arm/faults.hh Sat Sep 27 09:08:36 2014 -0400
@@ -181,10 +181,10 @@
// exception level
MiscRegIndex getFaultAddrReg64() const;
- void invoke(ThreadContext *tc,
- StaticInstPtr inst = StaticInst::nullStaticInstPtr);
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