[gem5-dev] changeset in gem5: arm: Use MiscRegIndex rather than int when fl...

[Andreas Hansson via gem5-dev]

changeset d469fdcd937e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d469fdcd937e
description:
        arm: Use MiscRegIndex rather than int when flattening

        Some additional type checking to avoid future issues.

diffstat:

 src/arch/arm/miscregs.cc     |  14 ++++++++------
 src/arch/arm/miscregs.hh     |   4 ++--
 src/arch/arm/table_walker.cc |   7 ++++---
 3 files changed, 14 insertions(+), 11 deletions(-)

diffs (71 lines):

diff -r cc13df09fa55 -r d469fdcd937e src/arch/arm/miscregs.cc
--- a/src/arch/arm/miscregs.cc  Wed Oct 01 08:05:51 2014 -0400
+++ b/src/arch/arm/miscregs.cc  Wed Oct 01 08:05:52 2014 -0400
@@ -2034,22 +2034,24 @@
 }
 
 int
-flattenMiscRegNsBanked(int reg, ThreadContext *tc)
+flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc)
 {
+    int reg_as_int = static_cast<int>(reg);
     if (miscRegInfo[reg][MISCREG_BANKED]) {
         SCR scr = tc->readMiscReg(MISCREG_SCR);
-        reg += (ArmSystem::haveSecurity(tc) && !scr.ns) ? 2 : 1;
+        reg_as_int += (ArmSystem::haveSecurity(tc) && !scr.ns) ? 2 : 1;
     }
-    return reg;
+    return reg_as_int;
 }
 
 int
-flattenMiscRegNsBanked(int reg, ThreadContext *tc, bool ns)
+flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns)
 {
+    int reg_as_int = static_cast<int>(reg);
     if (miscRegInfo[reg][MISCREG_BANKED]) {
-        reg += (ArmSystem::haveSecurity(tc) && !ns) ? 2 : 1;
+        reg_as_int += (ArmSystem::haveSecurity(tc) && !ns) ? 2 : 1;
     }
-    return reg;
+    return reg_as_int;
 }
 
 
diff -r cc13df09fa55 -r d469fdcd937e src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh  Wed Oct 01 08:05:51 2014 -0400
+++ b/src/arch/arm/miscregs.hh  Wed Oct 01 08:05:52 2014 -0400
@@ -1859,14 +1859,14 @@
     // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
     // for MCR/MRC instructions
     int
-    flattenMiscRegNsBanked(int reg, ThreadContext *tc);
+    flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc);
 
     // Flattens a misc reg index using the specified security state. This is
     // used for opperations (eg address translations) where the security
     // state of the register access may differ from the current state of the
     // processor
     int
-    flattenMiscRegNsBanked(int reg, ThreadContext *tc, bool ns);
+    flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns);
 
     // Takes a misc reg index and returns the root reg if its one of a set of
     // banked registers
diff -r cc13df09fa55 -r d469fdcd937e src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc      Wed Oct 01 08:05:51 2014 -0400
+++ b/src/arch/arm/table_walker.cc      Wed Oct 01 08:05:52 2014 -0400
@@ -1158,9 +1158,10 @@
 
         // LPAE always uses remapping of memory attributes, irrespective of the
         // value of SCTLR.TRE
-        int reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0;
-        reg     = flattenMiscRegNsBanked(reg, currState->tc, 
!currState->isSecure);
-        uint32_t mair = currState->tc->readMiscReg(reg);
+        MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0;
+        int reg_as_int = flattenMiscRegNsBanked(reg, currState->tc,
+                                                !currState->isSecure);
+        uint32_t mair = currState->tc->readMiscReg(reg_as_int);
         attr = (mair >> (8 * (attrIndx % 4))) & 0xff;
         uint8_t attr_7_4 = bits(attr, 7, 4);
         uint8_t attr_3_0 = bits(attr, 3, 0);
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