Hi Ajith, That sounds like a very ambitious goal (and a lot of work).
I¹d suggest the following intermediate steps: 1. Make sure the bits and pieces that are truly not ISA dependent are built once (not once per ISA as we do it today), and then put in a library (libmem.a, libdev.a etc) that is used by the various builds. I have made some first steps in this direction with http://reviews.gem5.org/r/2439/ and http://reviews.gem5.org/r/2440/. A lot of the code in src/mem src/base src/dev is actually ISA independent in the end and there is no point in building it over and over again. Ruby is an interesting one here as we do not only build it once per ISA, but also once per protocol. Perhaps some Ruby ninja has a good suggestion here for how to avoid this unfortunate crossproduct effect and build Ruby once for all protocols. 2. Build a single binary that is able to select the ISA at instantiation time (but still a single ISA). This will present some of the issues you mention, but perhaps we can rely on the namespaces rather than subclassing etc. I¹d say let¹s worry about this one once (1) is resolved. Hopefully this should not be too tricky. 3. What you suggest, mixed ISA simulation. The question you raise with the memory system and interconnect should not be a big issue from a basic data-movement point of view, but there may be issues when it comes to the consistency model. That said, I think there will be far bigger issues cropping up. Even simulating a single-ISA multi-core has its challenges... I¹m sure there are plenty people that would welcome these changes, so just shout if you get stuck. Andreas On 10/1/14, 9:32 PM, "Ajithchandra Saya via gem5-dev" <[email protected]> wrote: >Hi, > >We plan to create a ARM-x86 heterogeneous system for full system >simulation >to boot a heterogeneous operating system on top of it. I have started >looking at the gem5 code to try and understand the modifications needed. > >Please correct me if I am wrong. > >1. Currently the architecture selected is a compile time option. The base >classes (cpu,mem etc) also make lot of calls to architecture specific >namespaces which are resolved at compile time. So for a heterogeneous >system, we need to probably create multiple base classes or make it a run >time option ? >2. Do we have connectors (buses) to connect the heterogeneous CPU's and >other resources or do we need to create new ones? > >Please let me know which approach do you think is the best way to proceed. > > >Thanks in advance. > >Regards, >Ajith > >_______________________________________________ >gem5-dev mailing list >[email protected] >http://m5sim.org/mailman/listinfo/gem5-dev > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
