Hi Ahmed, Thanks for your willingness to attack this. We're glad to help out to the extent that we can.
The documentation on the wiki is a bit of a mess at this point; there was an effort to reorganize it that got stalled partway through, so sometimes there are two copies of certain documentation, and other times there is only one copy that's hard to find because it only exists under the old organization. So for example the partially reorganized new documentation on the ISA DSL is here: http://gem5.org/ISA_Parser but the older, more complete, but partially out of date (as in pre-x86) documentation is here: http://gem5.org/The_M5_ISA_description_language There's some extra information here as well: http://gem5.org/X86_Instruction_decoding Other than that, you just have to dig around in src/arch/x86/isa; I hope you've figured out the organization there. Sorry that there isn't more up front documentation, but if you've gone through all this and still have questions, feel free to fire away. Steve On Tue, Sep 30, 2014 at 9:44 AM, Ahmed Khawaja via gem5-dev < [email protected]> wrote: > Greetings, > > I am interested in adding full support for SSE and AVX to GEM5. I > have gone through all the documentation on the ISA DSL and looked at source > code, but I believe I am missing the level of understanding to begin adding > these instructions. I was wondering if there is some better resource than > just what is posted on the Wiki. Is there someone I could get in contact > with? This is in the scope of an academic project and I am fully interested > in submitting all of the code once completed. > > Thank you > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
