changeset 0caf62b57dfd in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=0caf62b57dfd
description:
ext: Add DRAMPower to enable on-line DRAM power modelling
This patch adds the open-source (BSD 3-clause) tool DRAMPower, commit
8d3cf4bbb10aa202d850ef5e5e3e4f53aa668fa6, to be built as a part of the
simulator. We have chosen this specific version of DRAMPower as it
provides the necessary functionality, and future updates will be
coordinated with the DRAMPower development team. The files added only
include the bits needed to build the library, thus excluding all
memory specifications, traces, and the stand-alone DRAMPower
command-line tool.
A future patch includes the DRAMPower functionality in the DRAM
controller, to enable on-line DRAM power modelling, and avoid using
post-processing of traces.
diffstat:
SConstruct | 4 +
ext/drampower/ChangeLog | 121 +++
ext/drampower/README.md | 298 +++++++++
ext/drampower/SConscript | 66 ++
ext/drampower/src/CmdScheduler.cc | 659 ++++++++++++++++++++
ext/drampower/src/CmdScheduler.h | 168 +++++
ext/drampower/src/CommandAnalysis.cc | 666 +++++++++++++++++++++
ext/drampower/src/CommandAnalysis.h | 213 ++++++
ext/drampower/src/MemArchitectureSpec.cc | 74 ++
ext/drampower/src/MemArchitectureSpec.h | 62 +
ext/drampower/src/MemCommand.cc | 159 +++++
ext/drampower/src/MemCommand.h | 170 +++++
ext/drampower/src/MemPowerSpec.cc | 107 +++
ext/drampower/src/MemPowerSpec.h | 77 ++
ext/drampower/src/MemTimingSpec.cc | 110 +++
ext/drampower/src/MemTimingSpec.h | 78 ++
ext/drampower/src/MemoryPowerModel.cc | 428 +++++++++++++
ext/drampower/src/MemoryPowerModel.h | 176 +++++
ext/drampower/src/MemorySpecification.cc | 60 +
ext/drampower/src/MemorySpecification.h | 239 +++++++
ext/drampower/src/Parameter.cc | 121 +++
ext/drampower/src/Parameter.h | 102 +++
ext/drampower/src/Parametrisable.cc | 133 ++++
ext/drampower/src/Parametrisable.h | 136 ++++
ext/drampower/src/TraceParser.cc | 120 +++
ext/drampower/src/TraceParser.h | 70 ++
ext/drampower/src/Utils.h | 64 ++
ext/drampower/src/libdrampower/LibDRAMPower.cc | 83 ++
ext/drampower/src/libdrampower/LibDRAMPower.h | 80 ++
ext/drampower/src/uncrustify.cfg | 280 ++++++++
ext/drampower/test/libdrampowertest/Makefile | 82 ++
ext/drampower/test/libdrampowertest/commands.trace | 19 +
ext/drampower/test/libdrampowertest/lib_test.cc | 122 +++
33 files changed, 5347 insertions(+), 0 deletions(-)
diffs (truncated from 5485 to 300 lines):
diff -r 26fee6c20087 -r 0caf62b57dfd SConstruct
--- a/SConstruct Thu Oct 09 17:52:00 2014 -0400
+++ b/SConstruct Thu Oct 09 17:52:03 2014 -0400
@@ -1175,6 +1175,10 @@
main.SConscript('ext/dramsim2/SConscript',
variant_dir = joinpath(build_root, 'dramsim2'))
+# DRAMPower build is shared across all configs in the build root.
+main.SConscript('ext/drampower/SConscript',
+ variant_dir = joinpath(build_root, 'drampower'))
+
###################################################
#
# This function is used to set up a directory with switching headers
diff -r 26fee6c20087 -r 0caf62b57dfd ext/drampower/ChangeLog
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/ext/drampower/ChangeLog Thu Oct 09 17:52:03 2014 -0400
@@ -0,0 +1,121 @@
+Change Log:
+
+DRAMPower v4.0 - * DRAMPower can now be compiled as a library. This enables a
user
+ to access the tool through an API and log commands and their
+ corresponding time stamps, removing the need to store large
+ command traces on disk. In addition, cycle counting
variables
+ have been changed to int64 to support longer simulations.
+ The library can be compiled without Xerces to remove an
optional
+ dependency and reduce the size of the binary.
+ * Improved robustness. The latest build is automatically
checked
+ out on a test server, compiled, and tested to verify that
the
+ output matches an expected reference. The code is also
compiled
+ with a large number of warning flags enabled and treats all
+ warnings as errors.
+ * Bug fix: Fixed bug in io/termination energy calculation.
+ * Bug fix: Fixed bug in calculation of auto precharge cycle.
+
+DRAMPower v3.1 - * Added IO and Termination Power measures from Micron's DRAM
Power
+ Calculator, for all supported DRAM generations. In the case
of
+ Wide IO DRAMs, these measures are already included in the
provided
+ current specifications. This feature enables support for
multi-rank
+ DRAM DIMMs (DDR2/3/4) and stacking of multiple Wide IO DRAM
dies
+ (equivalent to ranks). To indicate use of multi-rank DRAMs
or
+ multiple Wide IO DRAM dies/layers, the 'nbrOfRanks'
parameter in
+ the memory specification XMLs can be employed. Note: The
DRAM
+ command scheduler does not support multi-rank/multi-die
DRAMs yet.
+ Only the power estimation component of DRAMPower has been
updated
+ to support them. The current measures for dual-rank DRAMs
only
+ reflect those for the active rank and not the idle rank.
The
+ default state of the idle rank is assumed to be the same as
the
+ current memory state, for background power estimation.
Hence,
+ rank information in the command trace is not required.
+ * Added warning messages: New warning messages are provided,
to
+ identify if the memory or bank state is inconsistent in the
+ user-defined traces. Towards this, a state check is
performed on
+ every memory command issued.
+ * Improved run-time options: Users can now point directly to
the
+ memory specification XML, instead of just the memory ID.
Also,
+ users can optionally include IO and termination power
estimates
+ (for both single and dual rank DRAMs) using '-r' flag in
the
+ command line options.
+ * Bug fixes: (1) Refresh handler in the DRAM Command
Scheduler was
+ kept ON in the Self-Refresh mode, when it can be turned
OFF. This
+ bug has now been fixed. (2) Precharge All (PREA) always
considered
+ precharging of all banks. It has now been modified to
consider
+ precharging of the open/active banks alone.
+
+DRAMPower v3.0 - * Added support for LPDDR3 and DDR4 memories, besides the
already
+ supported DDR2/DDR3, LPDDR/LPDDR2 and WIDE IO DRAM
memories.
+ * Added DRAM Command Scheduler: To support users of
DRAMPower
+ without access to DRAM controllers, we have added a simple
DRAM
+ command scheduler that dynamically schedules DRAM commands
as if
+ it were a memory controller. The scheduler assumes
closed-page
+ policy, employs ASAP scheduling for DRAM commands (i.e.
schedules
+ commands as soon as timing constraints are met), performs
FCFS
+ scheduling on DRAM transactions and supports all the
different
+ DRAM generations supported by the power model. The
generated DRAM
+ command schedule is also analyzable for real-time
applications.
+ Users can also select speculative usage of power-down or
+ self-refresh modes (if needed) for idle periods between
+ transactions. It should be noted that using this command
scheduler
+ is optional and it can be (de-)selected during run-time and
users
+ can switch back to the previously used DRAM command
interface as
+ in the earlier versions.
+ * Improved run-time options: Users can specify the memory
and the
+ trace file to be used by DRAMPower using command line
options.
+ Additionally, if the DRAM command scheduler is being used,
the
+ users can specify the degree of bank interleaving required,
the
+ request size and power-down or self-refresh options. Also,
for
+ DDR4 memories the bank group interleaving can be specified
using
+ command line options.
+ * Bug fixes: (1) For command traces ending with a
RD/WR/RDA/WRA
+ command, the tool did not consider completion of operations
when
+ estimating the total trace energy. The missing cycles are
now
+ taken into account.
+ (2) The IDD5 (REF current) specification for WIDE IO SDR
memory
+ specifications only included 2 banks for refreshes instead
of all
+ four. We would like to thank David Roberts from AMD for
spotting
+ the issue in our DATE'13 article. These measures have been
updated.
+ (3) When estimating precharge cycle for commands with
+ auto-precharge, (RDA/WRA), the command analysis tool
employed the
+ last activation cycle in the entire DRAM instead of the
particular
+ DRAM bank. This bug has been fixed in this release.
+
+DRAMPower v2.1 - * Added support for variation-aware power estimation, for a
+ selection of DDR3 memories manufactured using 50nm process
+ technology, based on the Monte-Carlo analysis presented in
our
+ DAC'13 article.
+
+DRAMPower v2.0 - * Added support for LPDDR/LPDDR2 and WIDE IO DRAM memories,
besides
+ the already supported DDR2/DDR3 memories.
+ * Faster analysis: The trace analysis component in DRAMPower
v2.0
+ triggers the evaluation only during memory state
transitions
+ (between active, precharged, active and precharged
power-down,
+ refresh, self-refresh and power-up states) and not on
every clock
+ cycle, as was the case till the last version. This
optimization
+ speeds up the power simulations using DRAMPower by several
times
+ over cycle-accurate analysis, resulting in fast power
analysis,
+ without affecting the accuracy of the trace analysis or the
+ reported power and energy estimates.
+ * Verification effort: Our power model was verified by the
+ Microelectronic System Design group at TU Kaiserslautern
using
+ circuit-level SPICE simulations of a DRAM cross-section.
As a
+ result of this verification effort, a couple of power
equations
+ have been modified for Refresh and Self-refresh operations.
The
+ difference between the power and energy estimates reported
by our
+ updated model and the equivalent circuit-level simulations
is
+ < 2% for all memory operations of any granularity for all
memories
+ supported by DRAMPower.
+
+DRAMPower v1.2 - * Supports different power-down and self-refresh modes in
DDR2 and
+ DDR3 DRAM memories.
+ * Bug fix: Refresh power consumption equation in DRAMPower
v1,
+ incorrectly subtracted IDD2n (precharge background
current)
+ instead of IDD3n (active background current) from IDD5
(total
+ refresh current). This error has been rectified in this
version.
+
+DRAMPower v1.0 - * Performs cycle-accurate memory command trace analysis and
estimates
+ power and energy consumption numbers for the trace.
+ * It supports the basic memory operations like read, write,
refresh,
+ activate and (auto) precharge in DDR2 and DDR3 memories.
diff -r 26fee6c20087 -r 0caf62b57dfd ext/drampower/README.md
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/ext/drampower/README.md Thu Oct 09 17:52:03 2014 -0400
@@ -0,0 +1,298 @@
+# DRAM Power Model (DRAMPower)
+[](https://travis-ci.org/ravenrd/DRAMPower)
+[](https://coveralls.io/r/ravenrd/DRAMPower?branch=master)
+## 0. Releases
+
+The last official release can be found here:
+https://github.com/ravenrd/DRAMPower/releases/tag/4.0
+
+The master branch of the repository should be regarded as the bleeding-edge
version, which has all the latest features, but also all the latest bugs. Use
at your own discretion.
+
+## 1. Installation
+
+Clone the repository, or download the zip file of the release you would like
to use. The source code is available in src folder. src/cli/drampower.cc file
gives the user interface, where the user can specify the memory to be employed
and the command/transaction trace to be analyzed. To build, use:
+```bash
+make -j4
+```
+This command will download a set of trace files from
https://github.com/Sv3n/DRAMPowerTraces which can be used as test input for the
tool.
+
+## 2. Required Packages
+
+The tool was verified on Ubuntu 14.04 using:
+
+ * xerces-c (libxerces-c-dev) - v3.1 with Xerces development package
+ * gcc - v4.4.3
+
+## 3. Directory Structure
+ * src/: contains the source code of the DRAMPower tool that covers the power
model, the command scheduler and the trace analysis tool.
+ * memspecs/ : contains the memory specification XMLs, which give the
architectural, timing and current/voltage details for different DRAM memories.
+ * traces/ : contains 4 sample DRAM transaction traces and 1 sample
command trace (after the installation / compilation)
+ * test/ : contains test script and reference output
+
+## 4. Trace Specification
+### Command Traces
+If the command-level interface is being used, a command trace can be logged in
a file.
+An example is given in ```traces/commands.trace```
+
+The format it uses is: ```<timestamp>,<command>,<bank>```.
+For example, "500,ACT,2", where ACT is the command and 2 is the bank.
Timestamp is in clock cycles (cc), the list of supported commands is
+mentioned in src/MemCommand.h and the bank is the target bank number. For
non-bank-specific commands, bank can be set to 0. Rank need not be
+specified. The timing correctness of the trace is not verified by the tool and
is assumed to be accurate. However, warning messages are provided, to identify
if the memory or bank state is inconsistent in the trace. A sample command
trace is provided in the traces/ folder.
+
+### Transaction Traces
+If the transaction-level interface is being used, a transaction trace can be
logged.
+
+The format it uses is: ```<timestamp>,<transaction_type>,<address>```.
+For example, "35,READ,0x80028", where READ/WRITE can be the transaction type
and the logical address (32-bits long and byte addressable) less than the
maximum supported DRAM capacity of 4GB (32Gb).
+
+The tool uses a flexible and efficient memory map as follows: specified in HEX
(0x). Timestamp is in clock cycles (cc) and maximum
{row}-{bank}-{column}-{BI}-{BC}-{BGI}-{BL}
+Here, BI gives the degree of bank interleaving, BC gives the burst size
(count), BGI gives the degree of bank group interleaving (for DDR4) and BL
gives the burst length used by the device.
+Dual-Rank addressing is not yet supported. The BC and BL address bits are
derived from the column address bits, whereas the BI and BGI bits are derived
from the bank address bits.
+
+Four sample MediaBench application transaction traces have been provided. The
MediaBench applications include: (1) EPIC Encoder, (2) JPEG Encoder, (3) H263
Encoder and (4) MPEG2 Encoder. These applications were independently executed
on the SimpleScalar simulator with a 16KB L1 D-cache, 16KB L1 I-cache, 128KB L2
cache and 64-byte cache line configuration. We filtered out the L2 cache misses
meant for the DRAM and logged them as transaction traces. These can be used
with our command scheduler to generate equivalent command traces for any DRAM
memory specified.
+
+## 5. Usage
+
+src/cli/drampower.cc is the main interface file, which accepts user inputs to
specify memory to be employed and the command or transaction trace to be
analyzed. If the transaction trace (DRAM command scheduler) is being used, the
users can specify the degree of bank interleaving required, the request size
and the use of power-down or self-refresh options. Also, for DDR4 memories bank
group interleaving can be specified. Dual-rank DRAMs are not yet supported by
the command scheduler. Note: Speculative use of power-down or self-refresh
modes will increase the trace length due to the power-up latencies of these
power-saving modes.
+
+To use DRAMPower at the command-level (command trace), after make, use the
following:
+```bash
+./drampower -m <memory spec (ID)> -c <commands trace>
+```
+To use DRAMPower at the transaction-level (command scheduler), after make, use
the
+following:
+```bash
+./drampower -m <memory spec (ID)> -t <transactions trace>
+```
+Additional options when using transactions trace [-t] include:
+ * [-i] ```<interleaving>```
+ * [-s] ```<request size>```
+ * [-g] ```<DDR4 bank group interleaving>```
+ * [-p] ```<0 - No Power-Down, 1 - Power-Down, 2 - Self-Refresh>```
+
+Also, when using either the commands trace or the transactions trace, the user
can
+optionally include IO and Termination power estimates (obtained from Micron's
DRAM
+Power Calculator). To enable the same, the '-r' flag can be employed in
command line.
+
+If these options are not used, the default values assumed are:
+* interleaving = 1
+* request size = burst length * I/O width / 8 (in bytes) (from memory XMLs)
+* power saving = No power-down
+* bank group interleaving = 1
+* IO and termination = OFF (0)
+* Burst size (count) of 1
+
+## 6. Memory Specifications
+
+36 sample memory specifications are given in the XMLs targeting
DDR2/DDR3/DDR4, LPDDR/LPDDR2/LPDDR3 and WIDE IO DRAM devices. The memory
specifications are based on 1Gb DDR2, 1Gb & 2Gb DDR3, 2Gb LPDDR/LPDDR2 and 4Gb
DDR4/LPDDR3 Micron datasheets and the 256Mb Wide IO SDR specifications are
based on JEDEC timing specifications and circuit-level IDD measurements by TU
Kaiserslautern, inplace of the as yet unavailable vendor datasheets. 4 of the
memory specifications target dual-rank DDR3 DIMMs.
+
+Note: The timing specifications in the XMLs are in clock cycles (cc). The
current specifications for Reading and Writing do not include the I/O
consumption. They are computed and included seperately based on Micron Power
Calculator. The IDD measures associated with different power supply sources of
equal measure (VDD2, VDDCA and VDDQ) for LPDDR2, LPDDR3, DDR4 and WIDE IO
memories have been added up together for simplicity, since it does not impact
power computation accuracy. The current measures for dual-rank DIMMs reflect
only the measures for the active rank. The default state of the idle rank is
assumed to be the same as the complete memory state, for background power
estimation. Accordingly, in all dual-rank memory specifications, IDD2P0 has
been subtracted from the active currents and all background currents have been
halved. They are also accounted for seperately by the power model. Stacking
multiple Wide IO DRAM dies can also be captured by the nbrOfRanks parameter.
+
+## 7. Variation-aware Power And Energy Estimation
+
+15 of the included datasheets reflect the impact of process-variations on DRAM
currents for a selection of DDR3 memories manufactured at 50nm process
technology. These memories include:
+(1) MICRON_128MB_DDR3-1066_8bit - revision G
+(2) MICRON_128MB_DDR3-1066_16bit - revision G
+(3) MICRON_128MB_DDR3-1600_8bit - revision G
+(4) MICRON_256MB_DDR3-1066_8bit - revision D
+(5) MICRON_256MB_DDR3-1600_16bit - revision D
+
+The original vendor-provided datasheet current specifications are given in XMLs
+without suffixes such as _mu, _2s and _3s. XMLs including suffixes indicate
that the
+current measures are either: (1) typical (mu), or (2) include +2 sigma
variation (2s),
+or (3) include +3 sigma variation (3s). These measures are derived based on the
+Monte-Carlo analysis performed on our SPICE-based DRAM cross-section.
+
+To include these XMLs in your simulations, simply use them as the target
memory.
+
+## 8. Example Usage
+
+An example of using this tool is provided below. To compile the example,
+use the Makefile and make sure the Gcc and Xerces-c are installed. Then, run:
+```
+make -j4
+```
+
+This should show the following compilation message on the screen:
+```
+g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral
-Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF
src/xmlparser/MemSpecParser.d -iquote src -o src/xmlparser/MemSpecParser.o -c
src/xmlparser/MemSpecParser.cc
+g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral
-Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF
src/xmlparser/XMLHandler.d -iquote src -o src/xmlparser/XMLHandler.o -c
src/xmlparser/XMLHandler.cc
+g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral
-Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF
src/xmlparser/XMLParser.d -iquote src -o src/xmlparser/XMLParser.o -c
src/xmlparser/XMLParser.cc
+g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral
-Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF
src/CmdScheduler.d -iquote src -o src/CmdScheduler.o -c src/CmdScheduler.cc
+g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral
-Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF
src/CommandAnalysis.d -iquote src -o src/CommandAnalysis.o -c
src/CommandAnalysis.cc
+g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral
-Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF
src/MemArchitectureSpec.d -iquote src -o src/MemArchitectureSpec.o -c
src/MemArchitectureSpec.cc
+g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral
-Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF
src/MemCommand.d -iquote src -o src/MemCommand.o -c src/MemCommand.cc
+g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral
-Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF
src/MemoryPowerModel.d -iquote src -o src/MemoryPowerModel.o -c
src/MemoryPowerModel.cc
+g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral
-Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF
src/MemorySpecification.d -iquote src -o src/MemorySpecification.o -c
src/MemorySpecification.cc
+g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral
-Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF
src/MemPowerSpec.d -iquote src -o src/MemPowerSpec.o -c src/MemPowerSpec.cc
+g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral
-Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF
src/MemTimingSpec.d -iquote src -o src/MemTimingSpec.o -c src/MemTimingSpec.cc
+g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral
-Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF
src/Parameter.d -iquote src -o src/Parameter.o -c src/Parameter.cc
+g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral
-Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF
src/Parametrisable.d -iquote src -o src/Parametrisable.o -c
src/Parametrisable.cc
+g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral
-Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF
src/TraceParser.d -iquote src -o src/TraceParser.o -c src/TraceParser.cc
+g++ -O -W -pedantic-errors -Wextra -Werror -Wformat -Wformat-nonliteral
-Wpointer-arith -Wcast-align -Wconversion -g -std=c++98 -MMD -MF
src/libdrampower/LibDRAMPower.d -iquote src -o src/libdrampower/LibDRAMPower.o
-c src/libdrampower/LibDRAMPower.cc
+ar -cvr src/libdrampowerxml.a src/xmlparser/MemSpecParser.o
src/xmlparser/XMLHandler.o src/xmlparser/XMLParser.o
+a - src/xmlparser/MemSpecParser.o
+a - src/xmlparser/XMLHandler.o
+a - src/xmlparser/XMLParser.o
+g++ -Wall -o drampower src/xmlparser/MemSpecParser.o
src/xmlparser/XMLHandler.o src/xmlparser/XMLParser.o src/CmdScheduler.o
src/CommandAnalysis.o src/MemArchitectureSpec.o src/MemCommand.o
src/MemoryPowerModel.o src/MemorySpecification.o src/MemPowerSpec.o
src/MemTimingSpec.o src/Parameter.o src/Parametrisable.o src/TraceParser.o
-L/usr/lib -lxerces-c
+ar -cvr src/libdrampower.a src/CmdScheduler.o src/CommandAnalysis.o
src/MemArchitectureSpec.o src/MemCommand.o src/MemoryPowerModel.o
src/MemorySpecification.o src/MemPowerSpec.o src/MemTimingSpec.o
src/Parameter.o src/Parametrisable.o src/TraceParser.o
src/libdrampower/LibDRAMPower.o
+a - src/CmdScheduler.o
+a - src/CommandAnalysis.o
+a - src/MemArchitectureSpec.o
+a - src/MemCommand.o
+a - src/MemoryPowerModel.o
+a - src/MemorySpecification.o
+a - src/MemPowerSpec.o
+a - src/MemTimingSpec.o
+a - src/Parameter.o
+a - src/Parametrisable.o
+a - src/TraceParser.o
+a - src/libdrampower/LibDRAMPower.o
+```
+After this, run with the command trace or the transaction trace, as described
before:
+```
+./drampower -m memspecs/MICRON_1Gb_DDR3-1066_8bit_G.xml -t
traces/mediabench-epic.trace -r
+```
+The output should be something like this:
+
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