changeset 73b7549d979e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=73b7549d979e
description:
mem: Dynamically determine page bytes in memory components
This patch takes a step towards an ISA-agnostic memory
system by enabling the components to establish the page size after
instantiation. The swap operation in the memory is now also allowing
any granularity to avoid depending on the IntReg of the ISA.
diffstat:
src/mem/abstract_mem.cc | 23 ++++++++++++++---------
src/mem/abstract_mem.hh | 5 +++++
src/mem/cache/prefetch/Prefetcher.py | 2 +-
src/mem/cache/prefetch/base.cc | 9 ++++-----
src/mem/cache/prefetch/base.hh | 4 +++-
src/mem/cache/tags/base.cc | 1 -
src/mem/dram_ctrl.cc | 4 +++-
src/mem/dramsim2.cc | 2 ++
src/mem/ruby/common/Address.cc | 16 ----------------
src/mem/ruby/common/Address.hh | 2 --
src/mem/ruby/structures/Prefetcher.cc | 23 ++++++++++++++++-------
src/mem/ruby/structures/Prefetcher.hh | 6 ++++++
src/mem/ruby/structures/RubyPrefetcher.py | 3 +++
src/mem/simple_mem.cc | 2 ++
src/sim/system.cc | 2 --
src/sim/system.hh | 14 +++++++++++++-
16 files changed, 72 insertions(+), 46 deletions(-)
diffs (truncated from 423 to 300 lines):
diff -r a42b8d98fddc -r 73b7549d979e src/mem/abstract_mem.cc
--- a/src/mem/abstract_mem.cc Thu Oct 16 05:49:42 2014 -0400
+++ b/src/mem/abstract_mem.cc Thu Oct 16 05:49:43 2014 -0400
@@ -42,8 +42,8 @@
* Andreas Hansson
*/
-#include "arch/registers.hh"
-#include "config/the_isa.hh"
+#include <vector>
+
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/LLSC.hh"
@@ -59,7 +59,14 @@
confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map),
_system(NULL)
{
- if (size() % TheISA::PageBytes != 0)
+}
+
+void
+AbstractMemory::init()
+{
+ assert(system());
+
+ if (size() % _system->getPageBytes() != 0)
panic("Memory Size not divisible by page size\n");
}
@@ -327,19 +334,17 @@
uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
if (pkt->cmd == MemCmd::SwapReq) {
- TheISA::IntReg overwrite_val;
- bool overwrite_mem;
+ std::vector<uint8_t> overwrite_val(pkt->getSize());
uint64_t condition_val64;
uint32_t condition_val32;
if (!pmemAddr)
panic("Swap only works if there is real memory (i.e. null=False)");
- assert(sizeof(TheISA::IntReg) >= pkt->getSize());
- overwrite_mem = true;
+ bool overwrite_mem = true;
// keep a copy of our possible write value, and copy what is at the
// memory address into the packet
- std::memcpy(&overwrite_val, pkt->getPtr<uint8_t>(), pkt->getSize());
+ std::memcpy(&overwrite_val[0], pkt->getPtr<uint8_t>(), pkt->getSize());
std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
if (pkt->req->isCondSwap()) {
@@ -356,7 +361,7 @@
}
if (overwrite_mem)
- std::memcpy(hostAddr, &overwrite_val, pkt->getSize());
+ std::memcpy(hostAddr, &overwrite_val[0], pkt->getSize());
assert(!pkt->req->isInstFetch());
TRACE_PACKET("Read/Write");
diff -r a42b8d98fddc -r 73b7549d979e src/mem/abstract_mem.hh
--- a/src/mem/abstract_mem.hh Thu Oct 16 05:49:42 2014 -0400
+++ b/src/mem/abstract_mem.hh Thu Oct 16 05:49:43 2014 -0400
@@ -195,6 +195,11 @@
virtual ~AbstractMemory() {}
/**
+ * Initialise this memory.
+ */
+ void init();
+
+ /**
* See if this is a null memory that should never store data and
* always return zero.
*
diff -r a42b8d98fddc -r 73b7549d979e src/mem/cache/prefetch/Prefetcher.py
--- a/src/mem/cache/prefetch/Prefetcher.py Thu Oct 16 05:49:42 2014 -0400
+++ b/src/mem/cache/prefetch/Prefetcher.py Thu Oct 16 05:49:43 2014 -0400
@@ -67,7 +67,7 @@
"Let lower cache prefetcher train on prefetch requests")
inst_tagged = Param.Bool(True,
"Perform a tagged prefetch for instruction fetches always")
- sys = Param.System(Parent.any, "System this device belongs to")
+ sys = Param.System(Parent.any, "System this prefetcher belongs to")
class StridePrefetcher(BasePrefetcher):
type = 'StridePrefetcher'
diff -r a42b8d98fddc -r 73b7549d979e src/mem/cache/prefetch/base.cc
--- a/src/mem/cache/prefetch/base.cc Thu Oct 16 05:49:42 2014 -0400
+++ b/src/mem/cache/prefetch/base.cc Thu Oct 16 05:49:43 2014 -0400
@@ -47,9 +47,7 @@
#include <list>
-#include "arch/isa_traits.hh"
#include "base/trace.hh"
-#include "config/the_isa.hh"
#include "debug/HWPrefetch.hh"
#include "mem/cache/prefetch/base.hh"
#include "mem/cache/base.hh"
@@ -63,7 +61,8 @@
serialSquash(p->serial_squash), onlyData(p->data_accesses_only),
onMissOnly(p->on_miss_only), onReadOnly(p->on_read_only),
onPrefetch(p->on_prefetch), system(p->sys),
- masterId(system->getMasterId(name()))
+ masterId(system->getMasterId(name())),
+ pageBytes(system->getPageBytes())
{
}
@@ -312,9 +311,9 @@
}
bool
-BasePrefetcher::samePage(Addr a, Addr b)
+BasePrefetcher::samePage(Addr a, Addr b) const
{
- return roundDown(a, TheISA::PageBytes) == roundDown(b, TheISA::PageBytes);
+ return roundDown(a, pageBytes) == roundDown(b, pageBytes);
}
diff -r a42b8d98fddc -r 73b7549d979e src/mem/cache/prefetch/base.hh
--- a/src/mem/cache/prefetch/base.hh Thu Oct 16 05:49:42 2014 -0400
+++ b/src/mem/cache/prefetch/base.hh Thu Oct 16 05:49:43 2014 -0400
@@ -118,6 +118,8 @@
/** Request id for prefetches */
MasterID masterId;
+ const Addr pageBytes;
+
public:
Stats::Scalar pfIdentified;
@@ -172,7 +174,7 @@
/**
* Utility function: are addresses a and b on the same VM page?
*/
- bool samePage(Addr a, Addr b);
+ bool samePage(Addr a, Addr b) const;
public:
const Params*
params() const
diff -r a42b8d98fddc -r 73b7549d979e src/mem/cache/tags/base.cc
--- a/src/mem/cache/tags/base.cc Thu Oct 16 05:49:42 2014 -0400
+++ b/src/mem/cache/tags/base.cc Thu Oct 16 05:49:43 2014 -0400
@@ -46,7 +46,6 @@
* Definitions of BaseTags.
*/
-#include "config/the_isa.hh"
#include "cpu/smt.hh" //maxThreadsPerCPU
#include "mem/cache/tags/base.hh"
#include "mem/cache/base.hh"
diff -r a42b8d98fddc -r 73b7549d979e src/mem/dram_ctrl.cc
--- a/src/mem/dram_ctrl.cc Thu Oct 16 05:49:42 2014 -0400
+++ b/src/mem/dram_ctrl.cc Thu Oct 16 05:49:43 2014 -0400
@@ -225,7 +225,9 @@
void
DRAMCtrl::init()
{
- if (!port.isConnected()) {
+ AbstractMemory::init();
+
+ if (!port.isConnected()) {
fatal("DRAMCtrl %s is unconnected!\n", name());
} else {
port.sendRangeChange();
diff -r a42b8d98fddc -r 73b7549d979e src/mem/dramsim2.cc
--- a/src/mem/dramsim2.cc Thu Oct 16 05:49:42 2014 -0400
+++ b/src/mem/dramsim2.cc Thu Oct 16 05:49:43 2014 -0400
@@ -77,6 +77,8 @@
void
DRAMSim2::init()
{
+ AbstractMemory::init();
+
if (!port.isConnected()) {
fatal("DRAMSim2 %s is unconnected!\n", name());
} else {
diff -r a42b8d98fddc -r 73b7549d979e src/mem/ruby/common/Address.cc
--- a/src/mem/ruby/common/Address.cc Thu Oct 16 05:49:42 2014 -0400
+++ b/src/mem/ruby/common/Address.cc Thu Oct 16 05:49:43 2014 -0400
@@ -26,8 +26,6 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#include "arch/isa_traits.hh"
-#include "config/the_isa.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/system/System.hh"
@@ -136,20 +134,6 @@
return *this;
}
-void
-Address::makePageAddress()
-{
- m_address = maskLowOrderBits(TheISA::PageShift);
-}
-
-Address
-page_address(const Address& addr)
-{
- Address temp = addr;
- temp.makePageAddress();
- return temp;
-}
-
Address
next_stride_address(const Address& addr, int stride)
{
diff -r a42b8d98fddc -r 73b7549d979e src/mem/ruby/common/Address.hh
--- a/src/mem/ruby/common/Address.hh Thu Oct 16 05:49:42 2014 -0400
+++ b/src/mem/ruby/common/Address.hh Thu Oct 16 05:49:43 2014 -0400
@@ -69,7 +69,6 @@
physical_address_t getLineAddress() const;
physical_address_t getOffset() const;
void makeLineAddress();
- void makePageAddress();
void makeNextStrideAddress(int stride);
int64 memoryModuleIndex() const;
@@ -201,7 +200,6 @@
}
Address next_stride_address(const Address& addr, int stride);
-Address page_address(const Address& addr);
__hash_namespace_begin
template <> struct hash<Address>
diff -r a42b8d98fddc -r 73b7549d979e src/mem/ruby/structures/Prefetcher.cc
--- a/src/mem/ruby/structures/Prefetcher.cc Thu Oct 16 05:49:42 2014 -0400
+++ b/src/mem/ruby/structures/Prefetcher.cc Thu Oct 16 05:49:43 2014 -0400
@@ -45,7 +45,8 @@
m_unit_filter(p->unit_filter, Address(0)),
m_negative_filter(p->unit_filter, Address(0)),
m_nonunit_filter(p->nonunit_filter, Address(0)),
- m_prefetch_cross_pages(p->cross_page)
+ m_prefetch_cross_pages(p->cross_page),
+ m_page_shift(p->sys->getPageShift())
{
assert(m_num_streams > 0);
assert(m_num_startup_pfs <= MAX_PF_INFLIGHT);
@@ -231,12 +232,12 @@
}
// extend this prefetching stream by 1 (or more)
- Address page_addr = page_address(stream->m_address);
+ Address page_addr = pageAddress(stream->m_address);
Address line_addr = next_stride_address(stream->m_address,
stream->m_stride);
// possibly stop prefetching at page boundaries
- if (page_addr != page_address(line_addr)) {
+ if (page_addr != pageAddress(line_addr)) {
numPagesCrossed++;
if (!m_prefetch_cross_pages) {
// Deallocate the stream since we are not prefetching
@@ -295,7 +296,7 @@
mystream->m_type = type;
// create a number of initial prefetches for this stream
- Address page_addr = page_address(mystream->m_address);
+ Address page_addr = pageAddress(mystream->m_address);
Address line_addr = line_address(mystream->m_address);
Address prev_addr = line_addr;
@@ -303,7 +304,7 @@
for (int k = 0; k < m_num_startup_pfs; k++) {
line_addr = next_stride_address(line_addr, stride);
// possibly stop prefetching at page boundaries
- if (page_addr != page_address(line_addr)) {
+ if (page_addr != pageAddress(line_addr)) {
numPagesCrossed++;
if (!m_prefetch_cross_pages) {
// deallocate this stream prefetcher
@@ -382,11 +383,11 @@
alloc = false;
/// look for non-unit strides based on a (user-defined) page size
- Address page_addr = page_address(address);
+ Address page_addr = pageAddress(address);
Address line_addr = line_address(address);
for (uint32_t i = 0; i < m_num_nonunit_filters; i++) {
- if (page_address(m_nonunit_filter[i]) == page_addr) {
+ if (pageAddress(m_nonunit_filter[i]) == page_addr) {
// hit in the non-unit filter
// compute the actual stride (for this reference)
int delta = line_addr.getAddress() -
m_nonunit_filter[i].getAddress();
@@ -467,3 +468,11 @@
<< m_array[i].m_use_time << std::endl;
}
}
+
+Address
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