changeset 799c8ee4ecba in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=799c8ee4ecba
description:
arch: Use shared_ptr for all Faults
This patch takes quite a large step in transitioning from the ad-hoc
RefCountingPtr to the c++11 shared_ptr by adopting its use for all
Faults. There are no changes in behaviour, and the code modifications
are mostly just replacing "new" with "make_shared".
diffstat:
src/arch/alpha/ev5.cc
| 2 +-
src/arch/alpha/faults.hh
| 1 +
src/arch/alpha/interrupts.hh
| 4 +-
src/arch/alpha/isa/decoder.isa
| 26 +-
src/arch/alpha/isa/fp.isa
| 2 +-
src/arch/alpha/isa/opcdec.isa
| 2 +-
src/arch/alpha/isa/unimp.isa
| 2 +-
src/arch/alpha/isa/unknown.isa
| 2 +-
src/arch/alpha/tlb.cc
| 62 +-
src/arch/alpha/tlb.hh
| 1 -
src/arch/arm/insts/static_inst.hh
| 5 +-
src/arch/arm/interrupts.hh
| 19 +-
src/arch/arm/isa/formats/breakpoint.isa
| 3 +-
src/arch/arm/isa/formats/unimp.isa
| 6 +-
src/arch/arm/isa/insts/branch.isa
| 2 +-
src/arch/arm/isa/insts/branch64.isa
| 4 +-
src/arch/arm/isa/insts/data64.isa
| 24 +-
src/arch/arm/isa/insts/fp.isa
| 2 +-
src/arch/arm/isa/insts/macromem.isa
| 2 +-
src/arch/arm/isa/insts/misc.isa
| 83 ++-
src/arch/arm/isa/insts/misc64.isa
| 11 +-
src/arch/arm/isa/insts/neon.isa
| 13 +-
src/arch/arm/isa/insts/neon64.isa
| 3 +-
src/arch/arm/isa/insts/neon64_mem.isa
| 2 +-
src/arch/arm/isa/insts/swap.isa
| 3 +-
src/arch/arm/isa/templates/mem64.isa
| 2 +-
src/arch/arm/isa/templates/neon.isa
| 6 +-
src/arch/arm/isa/templates/vfp.isa
| 30 +-
src/arch/arm/table_walker.cc
| 222 +++++----
src/arch/arm/table_walker.hh
| 1 -
src/arch/arm/tlb.cc
| 121 +++--
src/arch/arm/tlb.hh
| 1 -
src/arch/arm/utility.cc
| 3 +-
src/arch/generic/memhelpers.hh
| 1 -
src/arch/mips/interrupts.cc
| 2 +-
src/arch/mips/isa.hh
| 1 -
src/arch/mips/isa/decoder.isa
| 18 +-
src/arch/mips/isa/formats/control.isa
| 10 +-
src/arch/mips/isa/formats/dsp.isa
| 8 +-
src/arch/mips/isa/formats/fp.isa
| 2 +-
src/arch/mips/isa/formats/int.isa
| 4 +-
src/arch/mips/isa/formats/mt.isa
| 6 +-
src/arch/mips/isa/formats/trap.isa
| 4 +-
src/arch/mips/isa/formats/unimp.isa
| 12 +-
src/arch/mips/isa/formats/unknown.isa
| 2 +-
src/arch/mips/mt.hh
| 6 +-
src/arch/mips/tlb.hh
| 1 -
src/arch/power/isa/formats/unimp.isa
| 2 +-
src/arch/power/isa/formats/unknown.isa
| 2 +-
src/arch/power/tlb.cc
| 2 +-
src/arch/power/tlb.hh
| 1 -
src/arch/sparc/interrupts.hh
| 18 +-
src/arch/sparc/isa/base.isa
| 2 +-
src/arch/sparc/isa/decoder.isa
| 84 +-
src/arch/sparc/isa/formats/mem/util.isa
| 12 +-
src/arch/sparc/isa/formats/priv.isa
| 4 +-
src/arch/sparc/isa/formats/trap.isa
| 2 +-
src/arch/sparc/isa/formats/unknown.isa
| 2 +-
src/arch/sparc/tlb.cc
| 52 +-
src/arch/sparc/tlb.hh
| 1 -
src/arch/sparc/utility.cc
| 2 +-
src/arch/sparc/utility.hh
| 1 -
src/arch/x86/interrupts.cc
| 14 +-
src/arch/x86/isa/formats/string.isa
| 2 +-
src/arch/x86/isa/formats/unknown.isa
| 2 +-
src/arch/x86/isa/insts/general_purpose/compare_and_test/bounds.py
| 6 +-
src/arch/x86/isa/insts/general_purpose/control_transfer/interrupts_and_exceptions.py
| 4 +-
src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
| 2 +-
src/arch/x86/isa/insts/system/undefined_operation.py
| 2 +-
src/arch/x86/isa/insts/x87/arithmetic/addition.py
| 4 +-
src/arch/x86/isa/insts/x87/arithmetic/subtraction.py
| 4 +-
src/arch/x86/isa/insts/x87/data_transfer_and_conversion/exchange.py
| 4 +-
src/arch/x86/isa/microops/debug.isa
| 3 +-
src/arch/x86/isa/microops/regop.isa
| 72 +-
src/arch/x86/memhelpers.hh
| 1 -
src/arch/x86/pagetable_walker.cc
| 10 +-
src/arch/x86/tlb.cc
| 22 +-
src/arch/x86/tlb.hh
| 1 -
src/arch/x86/vtophys.cc
| 1 -
src/base/types.hh
| 9 +-
src/cpu/base_dyn_inst.hh
| 1 -
src/cpu/exec_context.hh
| 1 -
src/cpu/inorder/inorder_dyn_inst.cc
| 3 +-
src/cpu/inorder/inorder_dyn_inst.hh
| 1 -
src/cpu/o3/dyn_inst_impl.hh
| 2 +-
src/cpu/o3/lsq_unit.hh
| 7 +-
src/cpu/o3/lsq_unit_impl.hh
| 17 +-
src/cpu/static_inst.hh
| 1 -
src/sim/fault_fwd.hh
| 41 -
src/sim/faults.hh
| 4 +-
src/sim/tlb.hh
| 1 -
91 files changed, 625 insertions(+), 553 deletions(-)
diffs (truncated from 3661 to 300 lines):
diff -r 4cbe53150053 -r 799c8ee4ecba src/arch/alpha/ev5.cc
--- a/src/arch/alpha/ev5.cc Thu Oct 16 05:49:49 2014 -0400
+++ b/src/arch/alpha/ev5.cc Thu Oct 16 05:49:51 2014 -0400
@@ -477,7 +477,7 @@
{
PCState pc = pcState();
if (!(pc.pc() & 0x3))
- return new UnimplementedOpcodeFault;
+ return std::make_shared<UnimplementedOpcodeFault>();
pc.npc(readMiscRegNoEffect(IPR_EXC_ADDR));
pcState(pc);
diff -r 4cbe53150053 -r 799c8ee4ecba src/arch/alpha/faults.hh
--- a/src/arch/alpha/faults.hh Thu Oct 16 05:49:49 2014 -0400
+++ b/src/arch/alpha/faults.hh Thu Oct 16 05:49:51 2014 -0400
@@ -48,6 +48,7 @@
virtual bool skipFaultingInstruction() {return false;}
virtual bool setRestartAddress() {return true;}
public:
+ virtual ~AlphaFault() {}
void invoke(ThreadContext * tc, const StaticInstPtr &inst =
StaticInst::nullStaticInstPtr);
virtual FaultVect vect() = 0;
diff -r 4cbe53150053 -r 799c8ee4ecba src/arch/alpha/interrupts.hh
--- a/src/arch/alpha/interrupts.hh Thu Oct 16 05:49:49 2014 -0400
+++ b/src/arch/alpha/interrupts.hh Thu Oct 16 05:49:51 2014 -0400
@@ -32,6 +32,8 @@
#ifndef __ARCH_ALPHA_INTERRUPT_HH__
#define __ARCH_ALPHA_INTERRUPT_HH__
+#include <memory>
+
#include "arch/alpha/faults.hh"
#include "arch/alpha/isa_traits.hh"
#include "base/compiler.hh"
@@ -176,7 +178,7 @@
DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
- return new InterruptFault;
+ return std::make_shared<InterruptFault>();
} else {
return NoFault;
}
diff -r 4cbe53150053 -r 799c8ee4ecba src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isa Thu Oct 16 05:49:49 2014 -0400
+++ b/src/arch/alpha/isa/decoder.isa Thu Oct 16 05:49:51 2014 -0400
@@ -120,7 +120,7 @@
// signed overflow occurs when operands have same sign
// and sign of result does not match.
if (Ra_sl<31:> == Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
- fault = new IntegerOverflowFault;
+ fault = std::make_shared<IntegerOverflowFault>();
Rc_sl = tmp;
}});
0x02: s4addl({{ Rc_sl = (Ra_sl << 2) + Rb_or_imm_sl; }});
@@ -132,7 +132,7 @@
// signed overflow occurs when operands have same sign
// and sign of result does not match.
if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
- fault = new IntegerOverflowFault;
+ fault = std::make_shared<IntegerOverflowFault>();
Rc = tmp;
}});
0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
@@ -146,7 +146,7 @@
// sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur
if (Ra_sl<31:> != Rb_or_imm_sl<31:> && tmp<31:> != Ra_sl<31:>)
- fault = new IntegerOverflowFault;
+ fault = std::make_shared<IntegerOverflowFault>();
Rc_sl = tmp;
}});
0x0b: s4subl({{ Rc_sl = (Ra_sl << 2) - Rb_or_imm_sl; }});
@@ -160,7 +160,7 @@
// sign bit of the subtrahend (Rb), i.e., if the initial
// signs are the *same* then no overflow can occur
if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
- fault = new IntegerOverflowFault;
+ fault = std::make_shared<IntegerOverflowFault>();
Rc = tmp;
}});
0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
@@ -313,7 +313,7 @@
// checking the upper 33 bits for all 0s or all 1s.
uint64_t sign_bits = tmp<63:31>;
if (sign_bits != 0 && sign_bits != mask(33))
- fault = new IntegerOverflowFault;
+ fault = std::make_shared<IntegerOverflowFault>();
Rc_sl = tmp<31:0>;
}}, IntMultOp);
0x60: mulqv({{
@@ -324,7 +324,7 @@
// the lower 64
if (!((hi == 0 && lo<63:> == 0) ||
(hi == mask(64) && lo<63:> == 1)))
- fault = new IntegerOverflowFault;
+ fault = std::make_shared<IntegerOverflowFault>();
Rc = lo;
}}, IntMultOp);
}
@@ -603,19 +603,19 @@
#if SS_COMPATIBLE_FP
0x0b: sqrts({{
if (Fb < 0.0)
- fault = new ArithmeticFault;
+ fault = std::make_shared<ArithmeticFault>();
Fc = sqrt(Fb);
}}, FloatSqrtOp);
#else
0x0b: sqrts({{
if (Fb_sf < 0.0)
- fault = new ArithmeticFault;
+ fault = std::make_shared<ArithmeticFault>();
Fc_sf = sqrt(Fb_sf);
}}, FloatSqrtOp);
#endif
0x2b: sqrtt({{
if (Fb < 0.0)
- fault = new ArithmeticFault;
+ fault = std::make_shared<ArithmeticFault>();
Fc = sqrt(Fb);
}}, FloatSqrtOp);
}
@@ -746,7 +746,7 @@
// checking the upper 33 bits for all 0s or all 1s.
uint64_t sign_bits = Fb_uq<63:31>;
if (sign_bits != 0 && sign_bits != mask(33))
- fault = new IntegerOverflowFault;
+ fault = std::make_shared<IntegerOverflowFault>();
Fc_uq = (Fb_uq<31:30> << 62) | (Fb_uq<29:0> << 29);
}});
@@ -854,7 +854,7 @@
&& xc->readMiscReg(IPR_ICM) != mode_kernel)) {
// invalid pal function code, or attempt to do privileged
// PAL call in non-kernel mode
- fault = new UnimplementedOpcodeFault;
+ fault = std::make_shared<UnimplementedOpcodeFault>();
} else {
// check to see if simulator wants to do something special
// on this PAL call (including maybe suppress it)
@@ -904,7 +904,7 @@
IprToMiscRegIndex[ipr_index] : -1;
if(miscRegIndex < 0 || !IprIsReadable(miscRegIndex) ||
miscRegIndex >= NumInternalProcRegs)
- fault = new UnimplementedOpcodeFault;
+ fault = std::make_shared<UnimplementedOpcodeFault>();
else
Ra = xc->readMiscReg(miscRegIndex);
}}, IsIprAccess);
@@ -919,7 +919,7 @@
IprToMiscRegIndex[ipr_index] : -1;
if(miscRegIndex < 0 || !IprIsWritable(miscRegIndex) ||
miscRegIndex >= NumInternalProcRegs)
- fault = new UnimplementedOpcodeFault;
+ fault = std::make_shared<UnimplementedOpcodeFault>();
else
xc->setMiscReg(miscRegIndex, Ra);
if (traceData) { traceData->setData(Ra); }
diff -r 4cbe53150053 -r 799c8ee4ecba src/arch/alpha/isa/fp.isa
--- a/src/arch/alpha/isa/fp.isa Thu Oct 16 05:49:49 2014 -0400
+++ b/src/arch/alpha/isa/fp.isa Thu Oct 16 05:49:51 2014 -0400
@@ -46,7 +46,7 @@
{
Fault fault = NoFault; // dummy... this ipr access should not fault
if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
- fault = new FloatEnableFault;
+ fault = std::make_shared<FloatEnableFault>();
}
return fault;
}
diff -r 4cbe53150053 -r 799c8ee4ecba src/arch/alpha/isa/opcdec.isa
--- a/src/arch/alpha/isa/opcdec.isa Thu Oct 16 05:49:49 2014 -0400
+++ b/src/arch/alpha/isa/opcdec.isa Thu Oct 16 05:49:51 2014 -0400
@@ -69,7 +69,7 @@
OpcdecFault::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
- return new UnimplementedOpcodeFault;
+ return std::make_shared<UnimplementedOpcodeFault>();
}
}};
diff -r 4cbe53150053 -r 799c8ee4ecba src/arch/alpha/isa/unimp.isa
--- a/src/arch/alpha/isa/unimp.isa Thu Oct 16 05:49:49 2014 -0400
+++ b/src/arch/alpha/isa/unimp.isa Thu Oct 16 05:49:51 2014 -0400
@@ -118,7 +118,7 @@
{
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
- return new UnimplementedOpcodeFault;
+ return std::make_shared<UnimplementedOpcodeFault>();
}
Fault
diff -r 4cbe53150053 -r 799c8ee4ecba src/arch/alpha/isa/unknown.isa
--- a/src/arch/alpha/isa/unknown.isa Thu Oct 16 05:49:49 2014 -0400
+++ b/src/arch/alpha/isa/unknown.isa Thu Oct 16 05:49:51 2014 -0400
@@ -49,7 +49,7 @@
{
panic("attempt to execute unknown instruction "
"(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
- return new UnimplementedOpcodeFault;
+ return std::make_shared<UnimplementedOpcodeFault>();
}
}};
diff -r 4cbe53150053 -r 799c8ee4ecba src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Thu Oct 16 05:49:49 2014 -0400
+++ b/src/arch/alpha/tlb.cc Thu Oct 16 05:49:51 2014 -0400
@@ -30,6 +30,7 @@
* Andrew Schultz
*/
+#include <memory>
#include <string>
#include <vector>
@@ -220,7 +221,8 @@
if (req->getPaddr() & PAddrUncachedBit43) {
// IPR memory space not implemented
if (PAddrIprSpace(req->getPaddr())) {
- return new UnimpFault("IPR memory space not implemented!");
+ return std::make_shared<UnimpFault>(
+ "IPR memory space not implemented!");
} else {
// mark request as uncacheable
req->setFlags(Request::UNCACHEABLE);
@@ -233,7 +235,8 @@
// we don't have a ROM and we don't want to try to fetch from a device
// register as we destroy any data that is clear-on-read.
if (req->isUncacheable() && itb)
- return new UnimpFault("CPU trying to fetch from uncached I/O");
+ return std::make_shared<UnimpFault>(
+ "CPU trying to fetch from uncached I/O");
}
return NoFault;
@@ -387,7 +390,7 @@
// verify that this is a good virtual address
if (!validVirtualAddress(req->getVaddr())) {
fetch_acv++;
- return new ItbAcvFault(req->getVaddr());
+ return std::make_shared<ItbAcvFault>(req->getVaddr());
}
@@ -398,7 +401,7 @@
if (ICM_CM(tc->readMiscRegNoEffect(IPR_ICM)) !=
mode_kernel) {
fetch_acv++;
- return new ItbAcvFault(req->getVaddr());
+ return std::make_shared<ItbAcvFault>(req->getVaddr());
}
req->setPaddr(req->getVaddr() & PAddrImplMask);
@@ -416,7 +419,7 @@
if (!entry) {
fetch_misses++;
- return new ItbPageFault(req->getVaddr());
+ return std::make_shared<ItbPageFault>(req->getVaddr());
}
req->setPaddr((entry->ppn << PageShift) +
@@ -428,7 +431,7 @@
(1 << ICM_CM(tc->readMiscRegNoEffect(IPR_ICM))))) {
// instruction access fault
fetch_acv++;
- return new ItbAcvFault(req->getVaddr());
+ return std::make_shared<ItbAcvFault>(req->getVaddr());
}
fetch_hits++;
@@ -437,7 +440,7 @@
// check that the physical address is ok (catch bad physical addresses)
if (req->getPaddr() & ~PAddrImplMask) {
- return new MachineCheckFault();
+ return std::make_shared<MachineCheckFault>();
}
return checkCacheability(req, true);
@@ -457,7 +460,9 @@
DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
req->getSize());
uint64_t flags = write ? MM_STAT_WR_MASK : 0;
- return new DtbAlignmentFault(req->getVaddr(), req->getFlags(), flags);
+ return std::make_shared<DtbAlignmentFault>(req->getVaddr(),
+ req->getFlags(),
+ flags);
}
if (PcPAL(req->getPC())) {
@@ -476,7 +481,9 @@
uint64_t flags = (write ? MM_STAT_WR_MASK : 0) |
MM_STAT_BAD_VA_MASK |
MM_STAT_ACV_MASK;
- return new DtbPageFault(req->getVaddr(), req->getFlags(), flags);
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