changeset dcf27c8220ac in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=dcf27c8220ac
description:
arch,x86,mem: Dynamically determine the ISA for Ruby store check
This patch makes the memory system ISA-agnostic by enabling the Ruby
Sequencer to dynamically determine if it has to do a store check. To
enable this check, the ISA is encoded as an enum, and the system
is able to provide the ISA to the Sequencer at run time.
diffstat:
src/SConscript | 12 +++++++
src/arch/x86/insts/microldstop.hh | 9 +-----
src/arch/x86/ldstflags.hh | 60 +++++++++++++++++++++++++++++++++++++++
src/mem/ruby/system/RubyPort.cc | 3 +-
src/mem/ruby/system/RubyPort.hh | 2 +-
src/mem/ruby/system/Sequencer.cc | 18 +++++------
src/sim/system.hh | 5 +++
7 files changed, 89 insertions(+), 20 deletions(-)
diffs (211 lines):
diff -r 73b7549d979e -r dcf27c8220ac src/SConscript
--- a/src/SConscript Thu Oct 16 05:49:43 2014 -0400
+++ b/src/SConscript Thu Oct 16 05:49:44 2014 -0400
@@ -379,8 +379,20 @@
''')
+ # create defines for the preprocessing and compile-time determination
for i,isa in enumerate(isas):
code('#define $0 $1', define(isa), i + 1)
+ code()
+
+ # create an enum for any run-time determination of the ISA, we
+ # reuse the same name as the namespaces
+ code('enum class Arch {')
+ for i,isa in enumerate(isas):
+ if i + 1 == len(isas):
+ code(' $0 = $1', namespace(isa), define(isa))
+ else:
+ code(' $0 = $1,', namespace(isa), define(isa))
+ code('};')
code('''
diff -r 73b7549d979e -r dcf27c8220ac src/arch/x86/insts/microldstop.hh
--- a/src/arch/x86/insts/microldstop.hh Thu Oct 16 05:49:43 2014 -0400
+++ b/src/arch/x86/insts/microldstop.hh Thu Oct 16 05:49:44 2014 -0400
@@ -41,20 +41,13 @@
#define __ARCH_X86_INSTS_MICROLDSTOP_HH__
#include "arch/x86/insts/microop.hh"
+#include "arch/x86/ldstflags.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
namespace X86ISA
{
- const Request::FlagsType SegmentFlagMask = mask(4);
- const int FlagShift = 4;
- enum FlagBit {
- CPL0FlagBit = 1,
- AddrSizeFlagBit = 2,
- StoreCheck = 4
- };
-
/**
* Base class for load and store ops
*/
diff -r 73b7549d979e -r dcf27c8220ac src/arch/x86/ldstflags.hh
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/x86/ldstflags.hh Thu Oct 16 05:49:44 2014 -0400
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2007 The Hewlett-Packard Development Company
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_X86_LDSTFLAGS_HH__
+#define __ARCH_X86_LDSTFLAGS_HH__
+
+#include "base/bitfield.hh"
+#include "mem/request.hh"
+
+/**
+ * This is exposed globally, independent of the ISA.
+ */
+namespace X86ISA
+{
+ const Request::FlagsType M5_VAR_USED SegmentFlagMask = mask(4);
+ const int FlagShift = 4;
+ enum FlagBit {
+ CPL0FlagBit = 1,
+ AddrSizeFlagBit = 2,
+ StoreCheck = 4
+ };
+}
+
+#endif //__ARCH_X86_LDSTFLAGS_HH__
diff -r 73b7549d979e -r dcf27c8220ac src/mem/ruby/system/RubyPort.cc
--- a/src/mem/ruby/system/RubyPort.cc Thu Oct 16 05:49:43 2014 -0400
+++ b/src/mem/ruby/system/RubyPort.cc Thu Oct 16 05:49:44 2014 -0400
@@ -52,13 +52,14 @@
RubyPort::RubyPort(const Params *p)
: MemObject(p), m_version(p->version), m_controller(NULL),
m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester),
+ system(p->system),
pioMasterPort(csprintf("%s.pio-master-port", name()), this),
pioSlavePort(csprintf("%s.pio-slave-port", name()), this),
memMasterPort(csprintf("%s.mem-master-port", name()), this),
memSlavePort(csprintf("%s-mem-slave-port", name()), this,
p->ruby_system, p->access_phys_mem, -1),
gotAddrRanges(p->port_master_connection_count), drainManager(NULL),
- system(p->system), access_phys_mem(p->access_phys_mem)
+ access_phys_mem(p->access_phys_mem)
{
assert(m_version != -1);
diff -r 73b7549d979e -r dcf27c8220ac src/mem/ruby/system/RubyPort.hh
--- a/src/mem/ruby/system/RubyPort.hh Thu Oct 16 05:49:43 2014 -0400
+++ b/src/mem/ruby/system/RubyPort.hh Thu Oct 16 05:49:44 2014 -0400
@@ -182,6 +182,7 @@
AbstractController* m_controller;
MessageBuffer* m_mandatory_q_ptr;
bool m_usingRubyTester;
+ System* system;
private:
void addToRetryList(MemSlavePort * port)
@@ -205,7 +206,6 @@
std::vector<PioMasterPort *> master_ports;
DrainManager *drainManager;
- System* system;
//
// Based on similar code in the M5 bus. Stores pointers to those ports
diff -r 73b7549d979e -r dcf27c8220ac src/mem/ruby/system/Sequencer.cc
--- a/src/mem/ruby/system/Sequencer.cc Thu Oct 16 05:49:43 2014 -0400
+++ b/src/mem/ruby/system/Sequencer.cc Thu Oct 16 05:49:44 2014 -0400
@@ -26,12 +26,9 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
+#include "arch/x86/ldstflags.hh"
#include "base/misc.hh"
#include "base/str.hh"
-#include "config/the_isa.hh"
-#if THE_ISA == X86_ISA
-#include "arch/x86/insts/microldstop.hh"
-#endif // X86_ISA
#include "cpu/testers/rubytest/RubyTester.hh"
#include "debug/MemoryAccess.hh"
#include "debug/ProtocolTrace.hh"
@@ -45,6 +42,7 @@
#include "mem/ruby/system/Sequencer.hh"
#include "mem/ruby/system/System.hh"
#include "mem/packet.hh"
+#include "sim/system.hh"
using namespace std;
@@ -630,13 +628,13 @@
if (pkt->req->isInstFetch()) {
primary_type = secondary_type = RubyRequestType_IFETCH;
} else {
-#if THE_ISA == X86_ISA
- uint32_t flags = pkt->req->getFlags();
- bool storeCheck = flags &
- (TheISA::StoreCheck << TheISA::FlagShift);
-#else
bool storeCheck = false;
-#endif // X86_ISA
+ // only X86 need the store check
+ if (system->getArch() == Arch::X86ISA) {
+ uint32_t flags = pkt->req->getFlags();
+ storeCheck = flags &
+ (X86ISA::StoreCheck << X86ISA::FlagShift);
+ }
if (storeCheck) {
primary_type = RubyRequestType_RMW_Read;
secondary_type = RubyRequestType_ST;
diff -r 73b7549d979e -r dcf27c8220ac src/sim/system.hh
--- a/src/sim/system.hh Thu Oct 16 05:49:43 2014 -0400
+++ b/src/sim/system.hh Thu Oct 16 05:49:44 2014 -0400
@@ -271,6 +271,11 @@
*/
bool isMemAddr(Addr addr) const;
+ /**
+ * Get the architecture.
+ */
+ Arch getArch() const { return Arch::TheISA; }
+
/**
* Get the page bytes for the ISA.
*/
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