[gem5-dev] changeset in gem5: cpu: o3: corrects base FP and CC register ind...

[Nilay Vaish via gem5-dev]

changeset 5914229e6b16 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=5914229e6b16
description:
        cpu: o3: corrects base FP and CC register index in removeThread()

diffstat:

 src/cpu/o3/cpu.cc |  12 ++++--------
 1 files changed, 4 insertions(+), 8 deletions(-)

diffs (34 lines):

diff -r 9b848f3813c5 -r 5914229e6b16 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Mon Oct 20 16:45:25 2014 -0500
+++ b/src/cpu/o3/cpu.cc Mon Oct 20 16:47:55 2014 -0500
@@ -835,26 +835,22 @@
     // Unbind Int Regs from Rename Map
     for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
         PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
-
         scoreboard.unsetReg(phys_reg);
         freeList.addReg(phys_reg);
     }
 
     // Unbind Float Regs from Rename Map
-    int max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
-    for (int freg = TheISA::NumIntRegs; freg < max_reg; freg++) {
+    int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
+    for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
         PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
-
         scoreboard.unsetReg(phys_reg);
         freeList.addReg(phys_reg);
     }
 
     // Unbind condition-code Regs from Rename Map
-    max_reg = TheISA::NumIntRegs + TheISA::NumFloatRegs + TheISA::NumCCRegs;
-    for (int creg = TheISA::NumIntRegs + TheISA::NumFloatRegs;
-         creg < max_reg; creg++) {
+    max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
+    for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) {
         PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
-
         scoreboard.unsetReg(phys_reg);
         freeList.addReg(phys_reg);
     }
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