[gem5-dev] changeset in gem5: arm, mem: Fix drain bug and provide drain pri...

[Ali Saidi via gem5-dev]

changeset d5554f97c451 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d5554f97c451
description:
        arm, mem: Fix drain bug and provide drain prints for more components.

diffstat:

 src/arch/arm/table_walker.cc |  5 ++---
 src/mem/cache/mshr_queue.cc  |  3 +++
 src/mem/dram_ctrl.cc         |  2 ++
 src/mem/simple_mem.cc        |  5 ++++-
 4 files changed, 11 insertions(+), 4 deletions(-)

diffs (105 lines):

diff -r aa46a8ae3487 -r d5554f97c451 src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc      Wed Oct 29 23:18:26 2014 -0500
+++ b/src/arch/arm/table_walker.cc      Wed Oct 29 23:18:26 2014 -0500
@@ -388,7 +388,6 @@
     // if we've still got pending translations schedule more work
     nextWalk(tc);
     currState = NULL;
-    completeDrain();
 }
 
 Fault
@@ -1677,7 +1676,6 @@
     doL1Descriptor();
 
     stateQueues[L1].pop_front();
-    completeDrain();
     // Check if fault was generated
     if (currState->fault != NoFault) {
         currState->transState->finish(currState->fault, currState->req,
@@ -1745,7 +1743,6 @@
 
 
     stateQueues[L2].pop_front();
-    completeDrain();
     pending = false;
     nextWalk(currState->tc);
 
@@ -1844,6 +1841,8 @@
 {
     if (pendingQueue.size())
         schedule(doProcessEvent, clockEdge(Cycles(1)));
+    else
+        completeDrain();
 }
 
 bool
diff -r aa46a8ae3487 -r d5554f97c451 src/mem/cache/mshr_queue.cc
--- a/src/mem/cache/mshr_queue.cc       Wed Oct 29 23:18:26 2014 -0500
+++ b/src/mem/cache/mshr_queue.cc       Wed Oct 29 23:18:26 2014 -0500
@@ -45,7 +45,9 @@
  * Definition of MSHRQueue class functions.
  */
 
+#include "base/trace.hh"
 #include "mem/cache/mshr_queue.hh"
+#include "debug/Drain.hh"
 
 using namespace std;
 
@@ -191,6 +193,7 @@
     if (drainManager && allocated == 0) {
         // Notify the drain manager that we have completed draining if
         // there are no other outstanding requests in this MSHR queue.
+        DPRINTF(Drain, "MSHRQueue now empty, signalling drained\n");
         drainManager->signalDrainDone();
         drainManager = NULL;
         setDrainState(Drainable::Drained);
diff -r aa46a8ae3487 -r d5554f97c451 src/mem/dram_ctrl.cc
--- a/src/mem/dram_ctrl.cc      Wed Oct 29 23:18:26 2014 -0500
+++ b/src/mem/dram_ctrl.cc      Wed Oct 29 23:18:26 2014 -0500
@@ -737,6 +737,7 @@
         // if there is nothing left in any queue, signal a drain
         if (writeQueue.empty() && readQueue.empty() &&
             drainManager) {
+            DPRINTF(Drain, "DRAM controller done draining\n");
             drainManager->signalDrainDone();
             drainManager = NULL;
         }
@@ -1290,6 +1291,7 @@
             } else {
                 // check if we are drained
                 if (respQueue.empty () && drainManager) {
+                    DPRINTF(Drain, "DRAM controller done draining\n");
                     drainManager->signalDrainDone();
                     drainManager = NULL;
                 }
diff -r aa46a8ae3487 -r d5554f97c451 src/mem/simple_mem.cc
--- a/src/mem/simple_mem.cc     Wed Oct 29 23:18:26 2014 -0500
+++ b/src/mem/simple_mem.cc     Wed Oct 29 23:18:26 2014 -0500
@@ -44,6 +44,7 @@
 
 #include "base/random.hh"
 #include "mem/simple_mem.hh"
+#include "debug/Drain.hh"
 
 using namespace std;
 
@@ -200,6 +201,7 @@
             reschedule(dequeueEvent,
                        std::max(packetQueue.front().tick, curTick()), true);
         } else if (drainManager) {
+            DPRINTF(Drain, "Drainng of SimpleMemory complete\n");
             drainManager->signalDrainDone();
             drainManager = NULL;
         }
@@ -240,7 +242,8 @@
     if (!packetQueue.empty()) {
         count += 1;
         drainManager = dm;
-    }
+        DPRINTF(Drain, "SimpleMemory Queue has requests, waiting to drain\n");
+     }
 
     if (count)
         setDrainState(Drainable::Draining);
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