changeset ca4438b6e39a in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=ca4438b6e39a
description:
tests: Update regressions for the new kernels and various preceeding
fixes.
diffstat:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
| 15 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr
| 1 +
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout
| 14 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
| 18 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
| 15 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
| 2 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
| 16 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
| 18 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
| 15 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
| 1 +
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
| 14 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
| 18 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
| 15 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr
| 5 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
| 10 +-
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt
| 18 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini
| 537 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simerr
| 39 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout
| 39 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt
| 4157 +++---
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal
| 0
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/config.ini
| 536 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simerr
| 33 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/simout
| 37 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
| 1902 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/system.terminal
| 0
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
| 537 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
| 61 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
| 52 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
| 2662 ++--
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
| 537 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
| 39 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
| 37 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
| 5688 +++++----
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
| 0
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
| 536 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
| 33 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
| 35 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 2606 ++--
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
| 0
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
| 538 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
| 51 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
| 14 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
| 3577 +++---
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal
| 0
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
| 537 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
| 46 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
| 12 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt
| 3802 +++---
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal
| 0
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
| 537 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
| 32 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
| 10 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt
| 2744 ++--
tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal
| 0
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
| 9 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
| 4 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
| 12 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
| 18 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
| 9 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
| 5 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
| 8 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt
| 18 +-
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
| 12 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
| 15 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
| 1 +
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
| 10 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
| 18 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
| 15 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
| 1 +
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
| 8 +-
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
| 18 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
| 536 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
| 34 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
| 35 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
| 2129 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
| 0
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
| 535 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
| 27 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
| 33 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
| 997 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
| 0
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
| 537 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
| 35 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
| 35 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
| 4700 ++++----
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
| 0
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
| 536 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
| 28 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
| 33 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 2041 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
| 0
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
| 536 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
| 27 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
| 10 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt
| 1391 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/system.terminal
| 0
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
| 9 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
| 1 +
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
| 8 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
| 18 +-
101 files changed, 25480 insertions(+), 21170 deletions(-)
diffs (truncated from 55254 to 300 lines):
diff -r b423e1d0735e -r ca4438b6e39a
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
Wed Oct 29 23:18:27 2014 -0500
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/config.ini
Wed Oct 29 23:18:29 2014 -0500
@@ -15,10 +15,10 @@
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
eventq_index=0
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
@@ -26,8 +26,8 @@
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/dist/binaries/ts_osfpal
+readfile=/work/gem5.latest/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
@@ -691,7 +691,7 @@
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -714,7 +714,7 @@
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
@@ -844,6 +844,7 @@
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
@@ -894,7 +895,7 @@
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.terminal]
diff -r b423e1d0735e -r ca4438b6e39a
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr Wed Oct
29 23:18:27 2014 -0500
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simerr Wed Oct
29 23:18:29 2014 -0500
@@ -1,3 +1,4 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (128 Mbytes)
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
diff -r b423e1d0735e -r ca4438b6e39a
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout Wed Oct
29 23:18:27 2014 -0500
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/simout Wed Oct
29 23:18:29 2014 -0500
@@ -1,14 +1,12 @@
-Redirecting stdout to
build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor/simout
-Redirecting stderr to
build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 7 2014 10:41:53
-gem5 started May 7 2014 10:52:34
-gem5 executing on cz3212c2d7
-command line: build/ALPHA/gem5.opt -d
build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re
tests/run.py
build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor
+gem5 compiled Oct 29 2014 09:12:51
+gem5 started Oct 29 2014 09:20:31
+gem5 executing on u200540-lin
+command line: build/ALPHA/gem5.opt -d
build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor -re
/work/gem5.latest/tests/run.py
build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-minor
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /arm/projectscratch/pd/sysrandd/dist/binaries/vmlinux
+info: kernel located at: /dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1885187323500 because m5_exit instruction encountered
+Exiting @ tick 1883224346500 because m5_exit instruction encountered
diff -r b423e1d0735e -r ca4438b6e39a
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
Wed Oct 29 23:18:27 2014 -0500
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt
Wed Oct 29 23:18:29 2014 -0500
@@ -4,11 +4,11 @@
sim_ticks 1883224346500 #
Number of ticks simulated
final_tick 1883224346500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 293967 #
Simulator instruction rate (inst/s)
-host_op_rate 293967 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9864607727 #
Simulator tick rate (ticks/s)
-host_mem_usage 317632 #
Number of bytes of host memory used
-host_seconds 190.91 #
Real time elapsed on the host
+host_inst_rate 279379 #
Simulator instruction rate (inst/s)
+host_op_rate 279379 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9375076807 #
Simulator tick rate (ticks/s)
+host_mem_usage 311380 #
Number of bytes of host memory used
+host_seconds 200.88 #
Real time elapsed on the host
sim_insts 56120453 #
Number of instructions simulated
sim_ops 56120453 #
Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 #
Voltage in Volts
@@ -409,8 +409,6 @@
system.iocache.cache_copies 0 #
number of cache copies performed
system.iocache.ReadReq_mshr_misses::tsunami.ide 173
# number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 173 #
number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552
# number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 41552
# number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 173
# number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 173 #
number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 173
# number of overall MSHR misses
@@ -425,16 +423,14 @@
system.iocache.overall_mshr_miss_latency::total 12136383
# number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1
# mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1
# mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1
# mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1
# mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1
# mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1
# mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1
# mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1
# mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890
# average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890
# average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide
60470.207379 # average WriteInvalidateReq mshr miss
latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60470.207379
# average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide
inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf
# average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890
# average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 70152.502890
# average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890
# average overall mshr miss latency
diff -r b423e1d0735e -r ca4438b6e39a
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
Wed Oct 29 23:18:27 2014 -0500
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
Wed Oct 29 23:18:29 2014 -0500
@@ -15,10 +15,10 @@
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
eventq_index=0
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/binaries/vmlinux
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
@@ -26,8 +26,8 @@
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh
+pal=/dist/binaries/ts_osfpal
+readfile=/work/gem5.latest/tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
@@ -1099,7 +1099,7 @@
[system.disk0.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.disk2]
@@ -1122,7 +1122,7 @@
[system.disk2.image.child]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/disks/linux-bigswap2.img
read_only=true
[system.dvfs_handler]
@@ -1287,6 +1287,7 @@
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
@@ -1337,7 +1338,7 @@
[system.simple_disk.disk]
type=RawDiskImage
eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/disks/linux-latest.img
read_only=true
[system.terminal]
diff -r b423e1d0735e -r ca4438b6e39a
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
Wed Oct 29 23:18:27 2014 -0500
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
Wed Oct 29 23:18:29 2014 -0500
@@ -1,5 +1,5 @@
+warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (128 Mbytes)
warn: Sockets disabled, not accepting terminal connections
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
-warn: Obsolete M5 ivlb instruction encountered.
diff -r b423e1d0735e -r ca4438b6e39a
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
Wed Oct 29 23:18:27 2014 -0500
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
Wed Oct 29 23:18:29 2014 -0500
@@ -1,15 +1,13 @@
-Redirecting stdout to
build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
-Redirecting stderr to
build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 21 2014 10:36:29
-gem5 started Jun 21 2014 13:05:58
-gem5 executing on phenom
-command line: build/ALPHA/gem5.opt -d
build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re
/home/stever/hg/m5sim.org/gem5/tests/run.py
build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
+gem5 compiled Oct 29 2014 09:12:51
+gem5 started Oct 29 2014 09:21:02
+gem5 executing on u200540-lin
+command line: build/ALPHA/gem5.opt -d
build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re
/work/gem5.latest/tests/run.py
build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux
+info: kernel located at: /dist/binaries/vmlinux
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
-info: Launching CPU 1 @ 121062000
-Exiting @ tick 1906207240000 because m5_exit instruction encountered
+info: Launching CPU 1 @ 119596000
+Exiting @ tick 1905067807000 because m5_exit instruction encountered
diff -r b423e1d0735e -r ca4438b6e39a
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Wed Oct 29 23:18:27 2014 -0500
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Wed Oct 29 23:18:29 2014 -0500
@@ -4,11 +4,11 @@
sim_ticks 1905067807000 #
Number of ticks simulated
final_tick 1905067807000 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 133407 #
Simulator instruction rate (inst/s)
-host_op_rate 133407 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4441980470 #
Simulator tick rate (ticks/s)
-host_mem_usage 322876 #
Number of bytes of host memory used
-host_seconds 428.88 #
Real time elapsed on the host
+host_inst_rate 163944 #
Simulator instruction rate (inst/s)
+host_op_rate 163944 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5458738398 #
Simulator tick rate (ticks/s)
+host_mem_usage 318552 #
Number of bytes of host memory used
+host_seconds 348.99 #
Real time elapsed on the host
sim_insts 57215334 #
Number of instructions simulated
sim_ops 57215334 #
Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 #
Voltage in Volts
@@ -739,8 +739,6 @@
system.iocache.cache_copies 0 #
number of cache copies performed
system.iocache.ReadReq_mshr_misses::tsunami.ide 177
# number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 177 #
number of ReadReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552
# number of WriteInvalidateReq MSHR misses
-system.iocache.WriteInvalidateReq_mshr_misses::total 41552
# number of WriteInvalidateReq MSHR misses
system.iocache.demand_mshr_misses::tsunami.ide 177
# number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 177 #
number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 177
# number of overall MSHR misses
@@ -755,16 +753,14 @@
system.iocache.overall_mshr_miss_latency::total 12381383
# number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1
# mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1
# mshr miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999952
# mshr miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999952
# mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::tsunami.ide 1
# mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1
# mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1
# mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1
# mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69951.316384
# average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 69951.316384
# average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide
60474.936465 # average WriteInvalidateReq mshr miss
latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60474.936465
# average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide
inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf
# average WriteInvalidateReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69951.316384
# average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 69951.316384
# average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69951.316384
# average overall mshr miss latency
diff -r b423e1d0735e -r ca4438b6e39a
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini Wed Oct
29 23:18:27 2014 -0500
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini Wed Oct
29 23:18:29 2014 -0500
@@ -15,10 +15,10 @@
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/binaries/console
eventq_index=0
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
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