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Review request for Default. Repository: gem5 Description ------- Note: This was orginally posted by Derek Hower as: http://reviews.m5sim.org/r/1622/ I've updated the patch to work with the tip of the repository and done some simple testing on it. Thanks, Marc Changeset 10501:d945f688d61f --------------------------- x86 isa: This patch attempts an implementation at mwait. Mwait works as follows: 1. A cpu monitors an address of interest (monitor instruction) 2. A cpu calls mwait - this loads the cache line into that cpu's cache. 3. The cpu goes to sleep. 4. When another processor requests write permission for the line, it is evicted from the sleeping cpu's cache. This eviction is forwarded to the sleeping cpu, which then wakes up. Diffs ----- configs/ruby/MESI_Two_Level.py 5e0a421e2031 configs/ruby/MESI_Three_Level.py 5e0a421e2031 configs/ruby/MI_example.py 5e0a421e2031 configs/ruby/MOESI_CMP_directory.py 5e0a421e2031 configs/ruby/MOESI_CMP_token.py 5e0a421e2031 configs/ruby/MOESI_hammer.py 5e0a421e2031 configs/ruby/Ruby.py 5e0a421e2031 src/arch/x86/isa/decoder/two_byte_opcodes.isa 5e0a421e2031 src/arch/x86/isa/formats/formats.isa 5e0a421e2031 src/arch/x86/isa/formats/monitor_mwait.isa PRE-CREATION src/cpu/SConscript 5e0a421e2031 src/cpu/base.hh 5e0a421e2031 src/cpu/base.cc 5e0a421e2031 src/cpu/base_dyn_inst.hh 5e0a421e2031 src/cpu/checker/cpu.hh 5e0a421e2031 src/cpu/exec_context.hh 5e0a421e2031 src/cpu/o3/cpu.hh 5e0a421e2031 src/cpu/o3/cpu.cc 5e0a421e2031 src/cpu/simple/atomic.hh 5e0a421e2031 src/cpu/simple/base.hh 5e0a421e2031 src/cpu/simple/base.cc 5e0a421e2031 src/cpu/simple/timing.hh 5e0a421e2031 src/cpu/simple/timing.cc 5e0a421e2031 Diff: http://reviews.gem5.org/r/2471/diff/ Testing ------- Thanks, Marc Orr _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
