changeset 7a3ad4b09ce4 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7a3ad4b09ce4
description:
ruby: single physical memory in fs mode
Both ruby and the system used to maintain memory copies. With the
changes
carried for programmed io accesses, only one single memory is required
for
fs simulations. This patch sets the copy of memory that used to reside
with the system to null, so that no space is allocated, but address
checks
can still be carried out. All the memory accesses now source and sink
values
to the memory maintained by ruby.
diffstat:
configs/example/fs.py | 15 +++++++--------
configs/example/ruby_direct_test.py | 2 +-
configs/example/ruby_mem_test.py | 8 +-------
configs/example/ruby_network_test.py | 4 +---
configs/example/ruby_random_test.py | 8 +-------
configs/example/se.py | 2 +-
configs/ruby/MESI_Three_Level.py | 17 ++++++++++++++++-
configs/ruby/MESI_Two_Level.py | 23 ++++++++++++++++++-----
configs/ruby/MI_example.py | 19 +++++++++++++++++--
configs/ruby/MOESI_CMP_directory.py | 28 +++++++++++++++++++++++++---
configs/ruby/MOESI_CMP_token.py | 27 +++++++++++++++++++++++----
configs/ruby/MOESI_hammer.py | 23 +++++++++++++++++++----
configs/ruby/Network_test.py | 2 +-
configs/ruby/Ruby.py | 5 +++--
src/mem/protocol/MESI_Two_Level-dma.sm | 5 -----
src/mem/protocol/MOESI_CMP_directory-dma.sm | 5 -----
src/mem/protocol/MOESI_CMP_token-dma.sm | 5 -----
src/mem/ruby/system/DMASequencer.cc | 23 ++++++++---------------
src/mem/ruby/system/DMASequencer.hh | 5 +----
src/mem/ruby/system/Sequencer.py | 5 +----
tests/configs/memtest-ruby.py | 2 +-
tests/configs/pc-simple-timing-ruby.py | 14 +++++++-------
tests/configs/rubytest-ruby.py | 2 +-
tests/configs/simple-timing-mp-ruby.py | 2 +-
tests/configs/simple-timing-ruby.py | 2 +-
25 files changed, 155 insertions(+), 98 deletions(-)
diffs (truncated from 700 to 300 lines):
diff -r 30e3715c9405 -r 7a3ad4b09ce4 configs/example/fs.py
--- a/configs/example/fs.py Thu Nov 06 00:55:09 2014 -0600
+++ b/configs/example/fs.py Thu Nov 06 05:41:44 2014 -0600
@@ -135,7 +135,10 @@
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
sys.exit(1)
- Ruby.create_system(options, test_sys, test_sys.iobus,
test_sys._dma_ports)
+ Ruby.create_system(options, True, test_sys, test_sys.iobus,
+ test_sys._dma_ports)
+ test_sys.physmem = [SimpleMemory(range = r, null = True)
+ for r in test_sys.mem_ranges]
# Create a seperate clock domain for Ruby
test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
@@ -160,13 +163,9 @@
cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
- test_sys.ruby._cpu_ports[i].access_phys_mem = True
-
- # Create the appropriate memory controllers
- # and connect them to the IO bus
- test_sys.mem_ctrls = [TestMemClass(range = r) for r in
test_sys.mem_ranges]
- for i in xrange(len(test_sys.mem_ctrls)):
- test_sys.mem_ctrls[i].port = test_sys.iobus.master
+ # Connect the ruby io port to the PIO bus,
+ # assuming that there is just one such port.
+ test_sys.iobus.master = test_sys.ruby._io_port.slave
else:
if options.caches or options.l2cache:
diff -r 30e3715c9405 -r 7a3ad4b09ce4 configs/example/ruby_direct_test.py
--- a/configs/example/ruby_direct_test.py Thu Nov 06 00:55:09 2014 -0600
+++ b/configs/example/ruby_direct_test.py Thu Nov 06 05:41:44 2014 -0600
@@ -109,7 +109,7 @@
options.requests,
generator = generator)
-Ruby.create_system(options, system)
+Ruby.create_system(options, False, system)
# Since Ruby runs at an independent frequency, create a seperate clock
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
diff -r 30e3715c9405 -r 7a3ad4b09ce4 configs/example/ruby_mem_test.py
--- a/configs/example/ruby_mem_test.py Thu Nov 06 00:55:09 2014 -0600
+++ b/configs/example/ruby_mem_test.py Thu Nov 06 05:41:44 2014 -0600
@@ -128,7 +128,7 @@
dma_ports = []
for (i, dma) in enumerate(dmas):
dma_ports.append(dma.test)
-Ruby.create_system(options, system, dma_ports = dma_ports)
+Ruby.create_system(options, False, system, dma_ports = dma_ports)
# Create a top-level voltage domain and clock domain
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
@@ -159,12 +159,6 @@
#
system.ruby._cpu_ports[i].deadlock_threshold = 5000000
- #
- # Ruby doesn't need the backing image of memory when running with
- # the tester.
- #
- system.ruby._cpu_ports[i].access_phys_mem = False
-
for (i, dma) in enumerate(dmas):
#
# Tie the dma memtester ports to the correct functional port
diff -r 30e3715c9405 -r 7a3ad4b09ce4 configs/example/ruby_network_test.py
--- a/configs/example/ruby_network_test.py Thu Nov 06 00:55:09 2014 -0600
+++ b/configs/example/ruby_network_test.py Thu Nov 06 05:41:44 2014 -0600
@@ -113,7 +113,7 @@
system.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = system.voltage_domain)
-Ruby.create_system(options, system)
+Ruby.create_system(options, False, system)
# Create a seperate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
@@ -125,8 +125,6 @@
# Tie the cpu test ports to the ruby cpu port
#
cpus[i].test = ruby_port.slave
- ruby_port.access_phys_mem = False
-
i += 1
# -----------------------
diff -r 30e3715c9405 -r 7a3ad4b09ce4 configs/example/ruby_random_test.py
--- a/configs/example/ruby_random_test.py Thu Nov 06 00:55:09 2014 -0600
+++ b/configs/example/ruby_random_test.py Thu Nov 06 05:41:44 2014 -0600
@@ -106,7 +106,7 @@
system.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = system.voltage_domain)
-Ruby.create_system(options, system)
+Ruby.create_system(options, False, system)
# Create a seperate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
@@ -137,12 +137,6 @@
#
ruby_port.using_ruby_tester = True
- #
- # Ruby doesn't need the backing image of memory when running with
- # the tester.
- #
- ruby_port.access_phys_mem = False
-
# -----------------------
# run simulation
# -----------------------
diff -r 30e3715c9405 -r 7a3ad4b09ce4 configs/example/se.py
--- a/configs/example/se.py Thu Nov 06 00:55:09 2014 -0600
+++ b/configs/example/se.py Thu Nov 06 05:41:44 2014 -0600
@@ -231,7 +231,7 @@
system.physmem = SimpleMemory(range=AddrRange(options.mem_size),
null = True)
options.use_map = True
- Ruby.create_system(options, system)
+ Ruby.create_system(options, False, system)
assert(options.num_cpus == len(system.ruby._cpu_ports))
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
diff -r 30e3715c9405 -r 7a3ad4b09ce4 configs/ruby/MESI_Three_Level.py
--- a/configs/ruby/MESI_Three_Level.py Thu Nov 06 00:55:09 2014 -0600
+++ b/configs/ruby/MESI_Three_Level.py Thu Nov 06 05:41:44 2014 -0600
@@ -56,7 +56,7 @@
caches private to clusters")
return
-def create_system(options, system, dma_ports, ruby_system):
+def create_system(options, full_system, system, dma_ports, ruby_system):
if buildEnv['PROTOCOL'] != 'MESI_Three_Level':
fatal("This script requires the MESI_Three_Level protocol to be
built.")
@@ -231,5 +231,20 @@
dir_cntrl_nodes + \
dma_cntrl_nodes
+ # Create the io controller and the sequencer
+ if full_system:
+ io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
+ ruby_system._io_port = io_seq
+ io_controller = DMA_Controller(version = len(dma_ports),
+ dma_sequencer = io_seq,
+ ruby_system = ruby_system)
+ ruby_system.io_controller = io_controller
+
+ # Connect the dma controller to the network
+ io_controller.responseFromDir = ruby_system.network.master
+ io_controller.requestToDir = ruby_system.network.slave
+
+ all_cntrls = all_cntrls + [io_controller]
+
topology = create_topology(all_cntrls, options)
return (cpu_sequencers, dir_cntrl_nodes, topology)
diff -r 30e3715c9405 -r 7a3ad4b09ce4 configs/ruby/MESI_Two_Level.py
--- a/configs/ruby/MESI_Two_Level.py Thu Nov 06 00:55:09 2014 -0600
+++ b/configs/ruby/MESI_Two_Level.py Thu Nov 06 05:41:44 2014 -0600
@@ -48,7 +48,7 @@
def define_options(parser):
return
-def create_system(options, system, dma_ports, ruby_system):
+def create_system(options, full_system, system, dma_ports, ruby_system):
if buildEnv['PROTOCOL'] != 'MESI_Two_Level':
fatal("This script requires the MESI_Two_Level protocol to be built.")
@@ -196,7 +196,8 @@
for i, dma_port in enumerate(dma_ports):
# Create the Ruby objects associated with the dma controller
dma_seq = DMASequencer(version = i,
- ruby_system = ruby_system)
+ ruby_system = ruby_system,
+ slave = dma_port)
dma_cntrl = DMA_Controller(version = i,
dma_sequencer = dma_seq,
@@ -204,19 +205,31 @@
ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
- exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
# Connect the dma controller to the network
dma_cntrl.responseFromDir = ruby_system.network.master
dma_cntrl.requestToDir = ruby_system.network.slave
-
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
dir_cntrl_nodes + \
dma_cntrl_nodes
+ # Create the io controller and the sequencer
+ if full_system:
+ io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
+ ruby_system._io_port = io_seq
+ io_controller = DMA_Controller(version = len(dma_ports),
+ dma_sequencer = io_seq,
+ ruby_system = ruby_system)
+ ruby_system.io_controller = io_controller
+
+ # Connect the dma controller to the network
+ io_controller.responseFromDir = ruby_system.network.master
+ io_controller.requestToDir = ruby_system.network.slave
+
+ all_cntrls = all_cntrls + [io_controller]
+
topology = create_topology(all_cntrls, options)
-
return (cpu_sequencers, dir_cntrl_nodes, topology)
diff -r 30e3715c9405 -r 7a3ad4b09ce4 configs/ruby/MI_example.py
--- a/configs/ruby/MI_example.py Thu Nov 06 00:55:09 2014 -0600
+++ b/configs/ruby/MI_example.py Thu Nov 06 05:41:44 2014 -0600
@@ -42,7 +42,7 @@
def define_options(parser):
return
-def create_system(options, system, dma_ports, ruby_system):
+def create_system(options, full_system, system, dma_ports, ruby_system):
if buildEnv['PROTOCOL'] != 'MI_example':
panic("This script requires the MI_example protocol to be built.")
@@ -173,7 +173,22 @@
dma_cntrl.requestToDir = ruby_system.network.master
dma_cntrl.responseFromDir = ruby_system.network.slave
+ all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
- all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
+ # Create the io controller and the sequencer
+ if full_system:
+ io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
+ ruby_system._io_port = io_seq
+ io_controller = DMA_Controller(version = len(dma_ports),
+ dma_sequencer = io_seq,
+ ruby_system = ruby_system)
+ ruby_system.io_controller = io_controller
+
+ # Connect the dma controller to the network
+ io_controller.responseFromDir = ruby_system.network.master
+ io_controller.requestToDir = ruby_system.network.slave
+
+ all_cntrls = all_cntrls + [io_controller]
+
topology = create_topology(all_cntrls, options)
return (cpu_sequencers, dir_cntrl_nodes, topology)
diff -r 30e3715c9405 -r 7a3ad4b09ce4 configs/ruby/MOESI_CMP_directory.py
--- a/configs/ruby/MOESI_CMP_directory.py Thu Nov 06 00:55:09 2014 -0600
+++ b/configs/ruby/MOESI_CMP_directory.py Thu Nov 06 05:41:44 2014 -0600
@@ -48,7 +48,7 @@
def define_options(parser):
return
-def create_system(options, system, dma_ports, ruby_system):
+def create_system(options, full_system, system, dma_ports, ruby_system):
if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
panic("This script requires the MOESI_CMP_directory protocol to be
built.")
@@ -192,7 +192,8 @@
# Create the Ruby objects associated with the dma controller
#
dma_seq = DMASequencer(version = i,
- ruby_system = ruby_system)
+ ruby_system = ruby_system,
+ slave = dma_port)
dma_cntrl = DMA_Controller(version = i,
dma_sequencer = dma_seq,
@@ -200,14 +201,35 @@
ruby_system = ruby_system)
exec("ruby_system.dma_cntrl%d = dma_cntrl" % i)
- exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i)
dma_cntrl_nodes.append(dma_cntrl)
+ # Connect the dma controller to the network
+ dma_cntrl.responseFromDir = ruby_system.network.master
+ dma_cntrl.reqToDir = ruby_system.network.slave
+ dma_cntrl.respToDir = ruby_system.network.slave
+
all_cntrls = l1_cntrl_nodes + \
l2_cntrl_nodes + \
dir_cntrl_nodes + \
dma_cntrl_nodes
+ # Create the io controller and the sequencer
+ if full_system:
+ io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system)
+ ruby_system._io_port = io_seq
+ io_controller = DMA_Controller(version = len(dma_ports),
+ dma_sequencer = io_seq,
+ ruby_system = ruby_system)
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