changeset 13312d6e1caf in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=13312d6e1caf
description:
ruby: coherence protocols: remove data block from dirctory entry
This patch removes the data block present in the directory entry
structure
of each protocol in gem5's mainline. Firstly, this is required for
moving
towards common set of memory controllers for classic and ruby memory
systems.
Secondly, the data block was being misused in several places. It was
being
used for having free access to the physical memory instead of calling
on the
memory controller.
From now on, the directory controller will not have a direct visibility
into
the physical memory. The Memory Vector object now resides in the
Memory Controller class. This also means that some significant changes
are
being made to the functional accesses in ruby.
diffstat:
src/mem/protocol/MESI_Three_Level-L0cache.sm | 21 ++-
src/mem/protocol/MESI_Three_Level-L1cache.sm | 21 ++-
src/mem/protocol/MESI_Two_Level-L1cache.sm | 21 ++-
src/mem/protocol/MESI_Two_Level-L2cache.sm | 21 ++-
src/mem/protocol/MESI_Two_Level-dir.sm | 52 ++------
src/mem/protocol/MESI_Two_Level-dma.sm | 11 +-
src/mem/protocol/MI_example-cache.sm | 21 ++-
src/mem/protocol/MI_example-dir.sm | 65 +++-------
src/mem/protocol/MI_example-dma.sm | 8 +-
src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 30 +++-
src/mem/protocol/MOESI_CMP_directory-L2cache.sm | 23 +++-
src/mem/protocol/MOESI_CMP_directory-dir.sm | 97 ++++----------
src/mem/protocol/MOESI_CMP_directory-dma.sm | 8 +-
src/mem/protocol/MOESI_CMP_token-L1cache.sm | 11 +-
src/mem/protocol/MOESI_CMP_token-L2cache.sm | 11 +-
src/mem/protocol/MOESI_CMP_token-dir.sm | 96 ++++++---------
src/mem/protocol/MOESI_CMP_token-dma.sm | 8 +-
src/mem/protocol/MOESI_hammer-cache.sm | 30 +++-
src/mem/protocol/MOESI_hammer-dir.sm | 128 ++++++++------------
src/mem/protocol/MOESI_hammer-dma.sm | 8 +-
src/mem/protocol/Network_test-cache.sm | 8 +-
src/mem/protocol/Network_test-dir.sm | 8 +-
src/mem/protocol/RubySlicc_Types.sm | 2 +
src/mem/ruby/slicc_interface/AbstractCacheEntry.hh | 7 +
src/mem/ruby/slicc_interface/AbstractController.hh | 3 +-
src/mem/ruby/slicc_interface/AbstractEntry.hh | 6 -
src/mem/ruby/structures/DirectoryMemory.cc | 2 -
src/mem/ruby/structures/DirectoryMemory.hh | 3 -
src/mem/ruby/structures/MemoryControl.hh | 4 +-
src/mem/ruby/structures/RubyMemoryControl.cc | 27 +++-
src/mem/ruby/structures/RubyMemoryControl.hh | 12 +-
src/mem/ruby/system/System.cc | 45 +------
32 files changed, 417 insertions(+), 401 deletions(-)
diffs (truncated from 1979 to 300 lines):
diff -r ca248520649f -r 13312d6e1caf
src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm Thu Nov 06 05:42:20
2014 -0600
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm Thu Nov 06 05:42:20
2014 -0600
@@ -205,13 +205,28 @@
return AccessPermission:NotPresent;
}
- DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+ void functionalRead(Address addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
- return tbe.DataBlk;
+ testAndRead(addr, tbe.DataBlk, pkt);
+ } else {
+ testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
+ }
+ }
+
+ int functionalWrite(Address addr, Packet *pkt) {
+ int num_functional_writes := 0;
+
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ num_functional_writes := num_functional_writes +
+ testAndWrite(addr, tbe.DataBlk, pkt);
+ return num_functional_writes;
}
- return getCacheEntry(addr).DataBlk;
+ num_functional_writes := num_functional_writes +
+ testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
+ return num_functional_writes;
}
void setAccessPermission(Entry cache_entry, Address addr, State state) {
diff -r ca248520649f -r 13312d6e1caf
src/mem/protocol/MESI_Three_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm Thu Nov 06 05:42:20
2014 -0600
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm Thu Nov 06 05:42:20
2014 -0600
@@ -205,13 +205,28 @@
return AccessPermission:NotPresent;
}
- DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+ void functionalRead(Address addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
- return tbe.DataBlk;
+ testAndRead(addr, tbe.DataBlk, pkt);
+ } else {
+ testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
+ }
+ }
+
+ int functionalWrite(Address addr, Packet *pkt) {
+ int num_functional_writes := 0;
+
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ num_functional_writes := num_functional_writes +
+ testAndWrite(addr, tbe.DataBlk, pkt);
+ return num_functional_writes;
}
- return getCacheEntry(addr).DataBlk;
+ num_functional_writes := num_functional_writes +
+ testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
+ return num_functional_writes;
}
void setAccessPermission(Entry cache_entry, Address addr, State state) {
diff -r ca248520649f -r 13312d6e1caf src/mem/protocol/MESI_Two_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm Thu Nov 06 05:42:20
2014 -0600
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm Thu Nov 06 05:42:20
2014 -0600
@@ -224,13 +224,28 @@
return AccessPermission:NotPresent;
}
- DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+ void functionalRead(Address addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
- return tbe.DataBlk;
+ testAndRead(addr, tbe.DataBlk, pkt);
+ } else {
+ testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
+ }
+ }
+
+ int functionalWrite(Address addr, Packet *pkt) {
+ int num_functional_writes := 0;
+
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ num_functional_writes := num_functional_writes +
+ testAndWrite(addr, tbe.DataBlk, pkt);
+ return num_functional_writes;
}
- return getCacheEntry(addr).DataBlk;
+ num_functional_writes := num_functional_writes +
+ testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
+ return num_functional_writes;
}
void setAccessPermission(Entry cache_entry, Address addr, State state) {
diff -r ca248520649f -r 13312d6e1caf src/mem/protocol/MESI_Two_Level-L2cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm Thu Nov 06 05:42:20
2014 -0600
+++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm Thu Nov 06 05:42:20
2014 -0600
@@ -212,13 +212,28 @@
return AccessPermission:NotPresent;
}
- DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+ void functionalRead(Address addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
- return tbe.DataBlk;
+ testAndRead(addr, tbe.DataBlk, pkt);
+ } else {
+ testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
+ }
+ }
+
+ int functionalWrite(Address addr, Packet *pkt) {
+ int num_functional_writes := 0;
+
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ num_functional_writes := num_functional_writes +
+ testAndWrite(addr, tbe.DataBlk, pkt);
+ return num_functional_writes;
}
- return getCacheEntry(addr).DataBlk;
+ num_functional_writes := num_functional_writes +
+ testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
+ return num_functional_writes;
}
void setAccessPermission(Entry cache_entry, Address addr, State state) {
diff -r ca248520649f -r 13312d6e1caf src/mem/protocol/MESI_Two_Level-dir.sm
--- a/src/mem/protocol/MESI_Two_Level-dir.sm Thu Nov 06 05:42:20 2014 -0600
+++ b/src/mem/protocol/MESI_Two_Level-dir.sm Thu Nov 06 05:42:20 2014 -0600
@@ -73,7 +73,6 @@
// DirectoryEntry
structure(Entry, desc="...", interface="AbstractEntry") {
State DirectoryState, desc="Directory state";
- DataBlock DataBlk, desc="data for the block";
MachineID Owner;
}
@@ -90,6 +89,8 @@
void allocate(Address);
void deallocate(Address);
bool isPresent(Address);
+ bool functionalRead(Packet *pkt);
+ int functionalWrite(Packet *pkt);
}
@@ -148,13 +149,22 @@
return AccessPermission:NotPresent;
}
- DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+ void functionalRead(Address addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
- return tbe.DataBlk;
+ testAndRead(addr, tbe.DataBlk, pkt);
+ } else {
+ memBuffer.functionalRead(pkt);
+ }
+ }
+
+ int functionalWrite(Address addr, Packet *pkt) {
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ testAndWrite(addr, tbe.DataBlk, pkt);
}
- return getDirectoryEntry(addr).DataBlk;
+ return memBuffer.functionalWrite(pkt);
}
void setAccessPermission(Address addr, State state) {
@@ -297,7 +307,6 @@
out_msg.OriginalRequestorMachId := in_msg.Requestor;
out_msg.MessageSize := in_msg.MessageSize;
out_msg.Prefetch := in_msg.Prefetch;
- out_msg.DataBlk := getDirectoryEntry(in_msg.Addr).DataBlk;
DPRINTF(RubySlicc, "%s\n", out_msg);
}
@@ -320,13 +329,6 @@
}
}
- action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") {
- peek(responseNetwork_in, ResponseMsg) {
- getDirectoryEntry(in_msg.Addr).DataBlk := in_msg.DataBlk;
- DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n",
- in_msg.Addr, in_msg.DataBlk);
- }
- }
//added by SS for dma
action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch
request") {
peek(requestNetwork_in, RequestMsg) {
@@ -336,7 +338,6 @@
out_msg.Sender := machineID;
out_msg.OriginalRequestorMachId := machineID;
out_msg.MessageSize := in_msg.MessageSize;
- out_msg.DataBlk := getDirectoryEntry(address).DataBlk;
DPRINTF(RubySlicc, "%s\n", out_msg);
}
}
@@ -358,25 +359,14 @@
}
}
- action(dw_writeDMAData, "dw", desc="DMA Write data to memory") {
- peek(requestNetwork_in, RequestMsg) {
- getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk,
addressOffset(in_msg.Addr), in_msg.Len);
- }
- }
-
action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip
writeback request") {
peek(requestNetwork_in, RequestMsg) {
enqueue(memQueue_out, MemoryMsg, to_mem_ctrl_latency) {
out_msg.Addr := address;
out_msg.Type := MemoryRequestType:MEMORY_WB;
out_msg.OriginalRequestorMachId := machineID;
- //out_msg.DataBlk := in_msg.DataBlk;
out_msg.DataBlk.copyPartial(in_msg.DataBlk, addressOffset(address),
in_msg.Len);
-
-
out_msg.MessageSize := in_msg.MessageSize;
- //out_msg.Prefetch := in_msg.Prefetch;
-
DPRINTF(RubySlicc, "%s\n", out_msg);
}
}
@@ -434,15 +424,6 @@
}
}
- action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from
TBE") {
- assert(is_valid(tbe));
- //getDirectoryEntry(address).DataBlk.copyPartial(tbe.DataBlk, tbe.Offset,
tbe.Len);
- getDirectoryEntry(address).DataBlk.copyPartial(tbe.DataBlk,
addressOffset(tbe.PhysicalAddress), tbe.Len);
-
-
- }
-
-
action(qw_queueMemoryWBRequest_partialTBE, "qwt", desc="Queue off-chip
writeback request") {
peek(responseNetwork_in, ResponseMsg) {
enqueue(memQueue_out, MemoryMsg, to_mem_ctrl_latency) {
@@ -493,7 +474,6 @@
}
transition(M, Data, MI) {
- m_writeDataToMemory;
qw_queueMemoryWBRequest;
k_popIncomingResponseQueue;
}
@@ -518,7 +498,6 @@
}
transition(I, DMA_WRITE, ID_W) {
- dw_writeDMAData;
qw_queueMemoryWBRequest_partial;
j_popIncomingRequestQueue;
}
@@ -545,7 +524,6 @@
transition(M_DRD, Data, M_DRDI) {
drp_sendDMAData;
- m_writeDataToMemory;
qw_queueMemoryWBRequest;
k_popIncomingResponseQueue;
}
@@ -563,13 +541,11 @@
}
transition(M_DWR, Data, M_DWRI) {
- m_writeDataToMemory;
qw_queueMemoryWBRequest_partialTBE;
k_popIncomingResponseQueue;
}
transition(M_DWRI, Memory_Ack, I) {
- dwt_writeDMADataFromTBE;
aa_sendAck;
da_sendDMAAck;
w_deallocateTBE;
diff -r ca248520649f -r 13312d6e1caf src/mem/protocol/MESI_Two_Level-dma.sm
--- a/src/mem/protocol/MESI_Two_Level-dma.sm Thu Nov 06 05:42:20 2014 -0600
+++ b/src/mem/protocol/MESI_Two_Level-dma.sm Thu Nov 06 05:42:20 2014 -0600
@@ -55,8 +55,9 @@
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