Thank you for the quick response! That solved all seg faults I have encountered so far - both X86 and ARM.
Cagdas On Nov 6, 2014, at 4:06 PM, Andrew Bardsley <[email protected]> wrote: > Cagdas, can you try adding the line: > > config_manager->startup() > > at line 268 in util/cxx_config/main.cc (after the loadState(checkpoint) line). > > I've tried your ARM example (superficially, on my home machine) and it seems > to fix the problem there with running 'hello' with your setup instructions. > The startup call corresponds to startup in simulate(...) in simulate.py which > is guarded by need_startup. I've obviously forgotten to include that call. > > The proximal error when switching to O3, BTW, was a lack of a call to > ROB<>::setActiveThreads because of the lack of a call to > Commit::startupStage() because of the lack of a call to O3::startup(). > > Let me know if that helps with all your failure cases. > > Thanks for showing up the problem > > - Andrew > ________________________________________ > From: gem5-dev [[email protected]] On Behalf Of Cagdas Dirik via > gem5-dev [[email protected]] > Sent: 06 November 2014 23:01 > To: Cagdas Dirik; Andreas Hansson; Ali Saidi; Default > Subject: Re: [gem5-dev] Review Request 2430: config: Add the ability to read > a config file using C++ and Python > >> On Nov. 6, 2014, 7:48 p.m., Cagdas Dirik wrote: >>> This patch seems to be broken for X86 when restoring from checkpoints. A >>> sample test crashes with segmentation fault. Here are the steps: >>> 0. Sample test program does int array manipulation and creates a checkpoint >>> before computation. >>> 1. Run in se mode with --cpu-type=atomic --mem-type=simple_mem to keep >>> things simple. This will create the checkpoint. >>> 2. Run in se mode with --cpu-type=atomic --mem-type=simple_mem -r 1 and it >>> will run fine. >>> 3. Now run >>> >>> gem5.opt.cxx m5out/config.ini -r m5out/cpt.XYZ >>> >>> and it will seg fault right away at: >>> >>> Simulate:: Entering event queue @ 7088000. Starting simulation... >>> EventQueue (MainEventQueue-0)::schedule event (Event_21) for >>> 18446744073709551615 >>> EventQueue (MainEventQueue-0)::serviceOne event named Event_8 at 7088500 >>> Program received signal SIGSEGV, Segmentation fault. >>> getPage (addr=4195355, this=0x0) at build/X86/cpu/decode_cache.hh:86 >>> 86 if (recent[0] != pageMap.end()) { >>> (gdb) >>> >>> Trying it with other cpu-type and other mem-type results in similar seg >>> faults. It looks like this patch is missing some state initialization or >>> some other checkpoint restore functionality for X86. >> >> Ali Saidi wrote: >> I assume it's working for you without restoring from checkpoints? >> >> The code looks like state is being restored, but we've only ever tested >> it with ARM although I'm not sure why there would be a difference. >> >> Cagdas Dirik wrote: >> Correct! > > In addition to X86, ARM also seg faulted switching to arm_detailed cpu after > restoring from checkpoint. Here are the steps: > > 0. Sample test program does int array manipulation and creates a checkpoint > before computation. > 1. Run in se mode with --cpu-type=atomic --mem-type=simple_mem to keep things > simple. This will create the checkpoint > 2. Run in se mode with --caches --l2cache --cpu-type=arm_detailed > --mem-type=simple_mem -r 1 > 3. Now run > > gem5.opt.cxx m5out/config.ini -r m5out/cpt.XYZ -c system.cpu > system.switch_cpus 10000 > > and it will seg fault soon (at about tick delta 48500) at: > > EventQueue (MainEventQueue-0)::serviceOne event named Event_82 at 3837000 > EventQueue (MainEventQueue-0)::schedule event (Event_82) for 3837500 > EventQueue (MainEventQueue-0)::serviceOne event named Event_82 at 3837500 > EventQueue (MainEventQueue-0)::schedule event (Event_82) for 3838000 > EventQueue (MainEventQueue-0)::serviceOne event named Event_82 at 3838000 > Program received signal SIGSEGV, Segmentation fault. > 0x00002aaaab3908e8 in ROB<O3CPUImpl>::updateHead (this=this@entry=0xa90438) > at build/ARM/cpu/o3/rob_impl.hh:413 > 413 list<ThreadID>::iterator threads = activeThreads->begin(); > (gdb) > > > - Cagdas > > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/2430/#review5439 > ----------------------------------------------------------- > > > On Oct. 9, 2014, 2:32 p.m., Andreas Hansson wrote: >> >> ----------------------------------------------------------- >> This is an automatically generated e-mail. To reply, visit: >> http://reviews.gem5.org/r/2430/ >> ----------------------------------------------------------- >> >> (Updated Oct. 9, 2014, 2:32 p.m.) >> >> >> Review request for Default. >> >> >> Repository: gem5 >> >> >> Description >> ------- >> >> Changeset 10440:faea9dd0b3b1 >> --------------------------- >> config: Add the ability to read a config file using C++ and Python >> >> This patch adds the ability to load in config.ini files generated from >> gem5 into another instance of gem5 built without Python configuration >> support. The intended use case is for configuring gem5 when it is a >> library embedded in another simulation system. >> >> A parallel config file reader is also provided purely in Python to >> demonstrate the approach taken and to provided similar functionality >> for as-yet-unknown use models. The Python configuration file reader >> can read both .ini and .json files. >> >> C++ configuration file reading: >> >> A command line option has been added for scons to enable C++ configuration >> file reading: --with-cxx-config >> >> There is an example in util/cxx_config that shows C++ configuration in >> action. >> util/cxx_config/README explains how to build the example. >> >> Configuration is achieved by the object CxxConfigManager. It handles >> reading object descriptions from a CxxConfigFileBase object which >> wraps a config file reader. The wrapper class CxxIniFile is provided >> which wraps an IniFile for reading .ini files. Reading .json files >> from C++ would be possible with a similar wrapper and a JSON parser. >> >> After reading object descriptions, CxxConfigManager creates >> SimObjectParam-derived objects from the classes in the (generated with this >> patch) directory build/ARCH/cxx_config >> >> CxxConfigManager can then build SimObjects from those SimObjectParams (in an >> order dictated by the SimObject-value parameters on other objects) and bind >> ports of the produced SimObjects. >> >> A minimal set of instantiate-replacing member functions are provided by >> CxxConfigManager and few of the member functions of SimObject (such as drain) >> are extended onto CxxConfigManager. >> >> Python configuration file reading (configs/example/read_config.py): >> >> A Python version of the reader is also supplied with a similar interface to >> CxxConfigFileBase (In Python: ConfigFile) to config file readers. >> >> The Python config file reading will handle both .ini and .json files. >> >> The object construction strategy is slightly different in Python from the C++ >> reader as you need to avoid objects prematurely becoming the children of >> other >> objects when setting parameters. >> >> Port binding also needs to be strictly in the same port-index order as the >> original instantiation. >> >> >> Diffs >> ----- >> >> SConstruct 148b96b7bc77 >> configs/example/read_config.py PRE-CREATION >> src/SConscript 148b96b7bc77 >> src/python/m5/SimObject.py 148b96b7bc77 >> src/python/m5/params.py 148b96b7bc77 >> src/sim/SConscript 148b96b7bc77 >> src/sim/cxx_config.hh PRE-CREATION >> src/sim/cxx_config.cc PRE-CREATION >> src/sim/cxx_config_ini.hh PRE-CREATION >> src/sim/cxx_config_ini.cc PRE-CREATION >> src/sim/cxx_manager.hh PRE-CREATION >> src/sim/cxx_manager.cc PRE-CREATION >> util/cxx_config/Makefile PRE-CREATION >> util/cxx_config/README PRE-CREATION >> util/cxx_config/main.cc PRE-CREATION >> util/cxx_config/stats.hh PRE-CREATION >> util/cxx_config/stats.cc PRE-CREATION >> >> Diff: http://reviews.gem5.org/r/2430/diff/ >> >> >> Testing >> ------- >> >> >> Thanks, >> >> Andreas Hansson >> >> > > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > > > -- IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. 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