[gem5-dev] changeset in gem5: arm: Fix timing wakeup with LLSC

[Ali Saidi via gem5-dev]

changeset d1dce0b728b6 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=d1dce0b728b6
description:
        arm: Fix timing wakeup with LLSC

diffstat:

 src/cpu/simple/timing.cc |  12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diffs (29 lines):

diff -r 66451b99f3e6 -r d1dce0b728b6 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc  Wed Nov 12 09:05:21 2014 -0500
+++ b/src/cpu/simple/timing.cc  Wed Nov 12 09:05:22 2014 -0500
@@ -243,6 +243,12 @@
 TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
 {
     RequestPtr req = pkt->req;
+
+    // We're about the issues a locked load, so tell the monitor
+    // to start caring about this address
+    if (pkt->isRead() && pkt->req->isLLSC()) {
+        TheISA::handleLockedRead(thread, pkt->req);
+    }
     if (req->isMmappedIpr()) {
         Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
         new IprEvent(pkt, this, clockEdge(delay));
@@ -792,12 +798,6 @@
         traceData = NULL;
     }
 
-    // the locked flag may be cleared on the response packet, so check
-    // pkt->req and not pkt to see if it was a load-locked
-    if (pkt->isRead() && pkt->req->isLLSC()) {
-        TheISA::handleLockedRead(thread, pkt->req);
-    }
-
     delete pkt->req;
     delete pkt;
 
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