Right now, I believe the bus topology for x86 is basically the same as it is for other ISAs, a memory bus with the CPUs and memory, a bridge on its default port (I think?), an IO bus on the other side of the bridge, a bunch of devices, and a catch all PCI config device on the default port of that bus.
This can lead to some minor confusion since accesses to unimplemented IO ports end up going to the PCI config catch all. For reads that's basically fine since the IO ports would return junk anyway, and 0xff is as good junk as anything else. On writes however, the PCI config device will panic, and it will claim somebody was trying to write to config space. I'm thinking it would be easier for somebody to tell what was going on if the IO bus had a bridge to another bus as its default port, and that had two devices on it, the PCI config catch all which was set to respond to addresses with the PCI config address prefix. I made up a fixed partitioning of the physical address space for all the various types of accesses (mem, IO, APIC, PCI config, interrupt messages), so PCI config space has well defined fixed boundaries in the physical address space. There would also be an IsaFake device backing the IO port range, although I might want to add something to warn_once on accesses to it so people know if somebody is trying to talk to a device that's not there. I'm not sure what would hang off the default port of that bus. Maybe nothing? Anyway, what do you guys think? Is there a better way to get the same effect? Gabe _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
